simulation of ideal frequency divider in cadence

hi all,

i want to divide the o/p freq of Quad-VCO i.e. 4.8 GHz into 2.4 GHz. for this purpose i need a freq divider ckt.

i saw the freq divider from RF library in cadence. it is containing 4 pins (pin, pout,nin, nout).

how to apply stimulus to this pins & check the o/p

what does nin & nout stands for?

I guess pin is the positive IN and nin is the negative IN, maybe that's diff input components.

thats right.. they r diff i/p pins

but the problem is "where we have to mention the freq division factor"

when i open the block there is option as........CDF parameter of view "use tools filter option" & blank

It's probably a verilog defined block and it should have verilog view in his library.Check the verilog code and see how it divides and change the divider ratio as you wish by changing the verilog code.

hi bigboss,

its not having verilog view in library...

only symbol view is present

is it necessary to have schematic view for simulation of veriloga code

No, it's not necessary to have schematic view of veriloga view.Namely, a verilog defined block consists of behavioural circuit and therefore it has code only.

Thank you for your reply..

How ever my divider is not working.. output is always at zero.

Do I need to change any thing in the code.

In the code you have taken n=2 ( Divide by 2?). I am going ahead with the same.

I have changed the vdd power supply to my vdd=5, VSS=0, dir=1,tt=0.01

I did not touched any of the remaining code. I created the symbol, and trying to simulate in the spectreRF. But my output is always at zero..


Please reply.