What's the reason for this abnormal PLL output spectrum?[hlp]

Hi everyone,

The PLL output spectrum seems abnormally wide as shown in the attachment. It's a 20 GHz PLL design with 92 MHz reference and 256 divider-N. Can anyone tell me the potential reason?

Thanks,

I cannot see any attachment, but an "abnormally wide" output spectrum from such PLO like yours can have two basic sources:
a. out of lock, the PLO is "searching", and the wide spectrum has narrow distances between the lines which change by spectrum analyzer setting. Check the reference signal power, frequency and stability.
b. interference on DC power line (or in the reference line), coming often from a switching C power supply and /or voltage regulator. For PLO's, use preferably a linear power supply, and check the voltage with a scope. Any interference with a voltage > 30-50 mV p-p can drive the phase noise high.

I used similar structures locked from references like yours, without problems. The only other than the nominal output frequency should be spaced by the reference (or reference divided) frequency. My PLOs used a multiplied reference; using a divider may complicate the optimum function.

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I cannot see any attachment, but an "abnormally wide" output spectrum from such PLO like yours can have two basic sources:
a. out of lock, the PLO is "searching", and the wide spectrum has narrow distances between the lines which change by spectrum analyzer setting. Check the reference signal power, frequency and stability.
b. interference on DC power line (or in the reference line), coming often from a switching C power supply and /or voltage regulator. For PLO's, use preferably a linear power supply, and check the voltage with a scope. Any interference with a voltage > 30-50 mV p-p can drive the phase noise high.

I used similar structures locked from references like yours, without problems. The only other than the nominal output frequency should be spaced by the reference (or reference divided) frequency. My PLOs used a multiplied reference; using a divider may complicate the optimum function.

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Now I can see the picture: it is a typical "out -of-lock" situation. Try to tune the microwave oscillator till it locks. If it does mot, check my answer a. above.

The spectrum is just as abnormal at open loop, i. e. applying a fixed DC voltage to the control input of the VCO?. If yes, then you are having a low frequency quenching on the oscillator, as in old superregenerative receivers. Decouplings, couplings time constants, strength of positive feedback and DC bias components may have an influence on this.

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Another hint: if the VCO is clean by itself, please check the prescaler input level. If too low, it may be dividing by an erratic value instead of the intended N. Many prescaler topologyes self-oscillte if poorly driven.

Hi, lw1ecp

I've made another chip with a 20 GHz VCO followed by two CML divide-by-2 frequency dividers, in which both the 20-24 GHz and 5-6 GHz output spectrum could be observed. It could be found that the VCO's tuning range and output spectrum are fine. The 5-6 GHz output is also fine. But I haven't check the output of the TSPC divider chain. For the PLL, when the feedback line from the loop filter is disconnected and a dc level is supplied into the VCO, the ouput is also clean without the abnormal behavior shown in the figure.

Thanks for your suggestion all the same.

sincerely,

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Hi jiripolivka,

Thanks for your consideration and suggestions.

After tuning the loop filter(an external 3rd order passive filter is used on the PCB outside the chip), locking phenomenon is achieved when the reference frequency is from 88.7 to 91 GHz. The output spectrums for 88.7,89,90,91 MHz reference are shown in the attachment.
1.For 88.7 and 90 MHz reference, the PLL output has spus located at 17.9 and 35.8 MHz which is not harmonic of the reference frequency.
2.For other reference freuquencies outside 88.7-91 MHz range, the PLL still ran out of lock.
3.As the tuning range of my VCO is 21.22-23.93 GHz with 0-1.5 V tuning voltage, the measured locking range is much smaller than the designed range.

By the way, my PFD input frequency is the same as reference. The external loop filter's bandwidth is set as 600kHz. When calculating the loop parameters, the VCO gain is set at 2.2 GHz/V. A 0-1.5 V rectangular pulse signal with 50% duty cycle and 1.8ns leading and trailing edge is used as the reference signal. This signal is generated by the Agilent 81110A pattern generator.

Could you give some further suggestions?

Thank you,

best regards,

Thank you for all the spectra! I think your task is difficult as you chose to pull the output RF frequency by reference input frequency. I used various profesionally built PLOs with external reference source.
To make a good PLO, I can see you have problems with noise and spurs which all depend on various pArameters.
The feedback loop with the divider or reference multiplier is quite level-dependent, and as the multiplier generates harmonics, they an produce "non-harmonic" spurs when the harmonic combine. Frequency dividers tend to oscillate (free-run) if the input power is out of the optimum range.
I would advise to proceed step-by-step. The easier way is to adjust your system for a single-frequency output and single reference input. Check the spectrum for the varying reference input level and keep it at an optimum. If all is fine, then I would try to pull the RF output by varying the reference input. You will see some anomalies for sure.
The PLO Phase detector also generates its spurs due to a high multiplication (and harmonics). Maybe inter-stage filtering can help to reduce unwanted frequency combination.

Good luck!