PCB Crosstalk Compensation

I have recently been tasked with designing PCB's for Ethernet Connectors.
This can either be a PCB internally within the connector, or a PCB where the RJ45 Jack is mounted.
Most PCB's are Double sided and the internal version has no GND.

In both cases, it seems that using interdigitated capacitors i.e. finger tracks between certain pins can help compensate for NEXT and FEXT coming from the Connectors.

I noticed a thread raised a while back that touched on this subject, but not much info:-
https://www.edaboard.com/thread110547.html

Does anybody have any knowledge of how to make these calculations for the compensation on the PCB?
There seems to be a lot of Patents out there for this type of technology


Regards,

Before discussing solutions, what's the problem?
In which situations see you PCB crosstalk of ethernet signals with an significant amount related to the cable specification?
If so, can you mention a few patent numbers?

Here is an example Patent:-
http://www.google.com/patents/USRE43366

I guess the problem is knowing how much compensation to apply to the pins on the PCB when trying to meet CAT 6A and above.
There is Compensation applied at the input and output pins so to speak.
The related spec would be TIA-568B or IEC equivalent.