Phase Noise Measurement
I designed a 4 GHz VCRO in 0.18um cmos process with a phase noise of -111 dBc/Hz at 10 MHz offset frequency. In measuring phase noise, why is it measured usually in 10 MHz offset frequency?
Any idea? Thanks!
This is your specification, with an offset to measure phase noise far away from the carrier. Other phase noise specs can have values at other offset from the carrier (e.g. 1kHz).
Not usually...
System Architecture who decided PN specs. for a Tx/Rx system has defined this off-set from the requirements of this sytem.For instance 10kHz or 100kHz or other offsets can also be used regarding to modulation,selectivity and other system charateristics.
the only system I now of that only cares about 10 MHz offset phase noise only would be an optical system, like a sonnet clock. that is because they are mostly concerned with leading edge time jitter, and when you integrate up phase noise from 1 Hz to 1 MHz, it really is not that relevant compared to phase nose integrated from 1 MHz to 20 MHz. there are a lot more Hz of bandwidth in the later.
and even IF you did care a little about closer in phase noise, there is usually a carrier tracking filter somewhere that effectively highpass filters the jitter caused by it...eliminating it.
Bigboss is right. The system engineer should determine the PN, which is related to telecommunications system BER. For Radar, the PN is the most important.
Frankly speaking, -111dBc/Hz at 10 MHz offset is bad.
Most of the VCOs get about -130dBc/Hz at those frequency offset.
Phase noise is not a number but a spectrum extending from the carrier up to several MHz and farther. In various systems, PN values at 10 Hz, 100 Hz,,... 10 MHz are important.
If you measure the PN spectrum, you should notice that the shape is triangular, with peaks at some points. Those peaks are generated by mechanical vibrations, AC rectifier harmonics from DC power supply, also by pickup signals from the "ether".
When a VCO is used in a PLL system, then feedback error-voltage filter should be designed to reduce PN at frequencies important for the particular system where it is used.
A special care should be devoted to DC power supply and regulator- using switching power supplies is particularly harmful.
Using only one PN value at a single offset can be confusing and often is an error in design.