Negative resistance oscillator, how to get rid of wrong highfrequency of oscillation?

I am following RF design book and tutorials on negative resistance oscillator, but encounter some problems.

My design is 5GHz oscillator. I want to use single device, so i decided to use NE3210S01, it has very high gain, there are many papers with push-push, etc. oscillators, where NE3210S01 fundamental oscillation is at 3...9 GHz. My idea is that this device can give good harmonic level at 10GHz.

So i use this approach: take s-parameters at 5GHz, check for stability factors, add inductance if needed, update S-parameters in new configuration. Then choose Gsource near to inverse of S11, calculate Gout and decide Gload, correct Gload. Check that Gsource and Gload are in unstable regions. Problem is that in transient simulations i currently obtain some unwanted result like 11 to 15 GHz.
So it looks like Gin*Gs=1, Gout*Gload=1, k<1 conditions are matched at those higher frequencies.

I came to a conclusion, that i must draw all stability circles from 1 to 20 GHz, and draw Gload-Gsource impedance points too, and check all frequencies for instability. Actually there must be some wide band analysis, like building stable LNA. But it is pretty odd, because i come to conclusion that series and shunt resistances must be added to make transistor stable at 9..15GHz. Why i think it is strange, because authors who used NE3210S01 in oscillators (push-push, etc.) did not use any series resistances. I am pretty sure that transient simulation is correct, because it gives good results for book examples. Also gain and unstability factor at frequencies above 10GHz is too high.

What tools would you use to analyze such oscillator problems?

you can chose a transistor with a little less high frequency gain. Or you can do something to resistively shunt energy to a load at high frequency. The problem is you get small microresonances in things like bias lines, etc, and they can make the device latch on and oscillate at those high frequencies. You need to kill the system gain at the high frequency somehow

I tried configuration without inductive stub (common source), and high frequency oscillation disappeared.
What analysis i can do to ensure that wrong frequency does not occur?
Should i check all Gs, Gl, stability circles, stability factor for all frequencies up to Ft (Ft/2?).
Or maybe check negative resistance value for all frequencies?

I ensured that oscillator is at least conditionnaly stable at all unwanted frequencies. I did it by choosing source and load imedances in a such way, that they are pretty far away from unstable borders over frequency range 1-20GHz. I found out very interesting thing, that by calculating all distances on a smith chart it is possible to analyze manufacturing tolerances influence on stability (by building plots of those distances). For example, if some resistor or inductance value varies, circuit can become unstable. Plotting such distances gives frequency "peaks" where attention must be paid. So i optimized it till point, that there is very good negative resistance at 5GHz, reflection coefficient meeting oscillation condition, but oscillator does not work. Then i learned about nyquist plots, and that mine goes in counter clockwise direction or does not include 1+j*0 point, which does not satisfy oscillation criteria.

Plotting the stability circles for the provided S-parameters of NE3210S01 can be seen that the transistor is potential unstable in 1GHz-7GHz frequency range.
Making stable to use as an LNA perhaps is not a problem, but to make it stable and then to make it oscillating could be a challenge.

Maybe i am overthinking it:
I want to eliminate common source vias (problems with PCB thikness fr4 tolerances, via size/conductance tolerances). I feel vias will give problem, because small variation of source to ground path length leads to rapid movement of stability circles to the point where ~10..14GHz oscillations occur. So all negative resistance design fails when i make small variations of source-to gnd path. Although it seems that very good 10GHz negative resistance oscillator is possible that way.
To eliminate vias, i want to use open source stub with thin biasing line with quarterwave stub to ground.
I like ne3210s01's high gain, so going to try a little more.
here is my old 2015's experiment on S-parameters:
https://www.edaboard.com/attachments...0445-smith.png
https://www.edaboard.com/thread339788.html
there was an annoying problem: small rounding errors can lead to huge stability circle movement.
Now i ever thinking about putting varactor not only in gate network, but also on source pin to make design more flexible.

Very interesting:
also i readed https://www.highbeam.com/doc/1G1-56015068.html

And:
Pretty interesting reading. Many RF books do not mention Nyquist stability criteria.

Almost the entire book "Discrete Oscillator Design" written by Randal Rhea is based on this concept:

http://www.amazon.com/Discrete-Oscil.../dp/1608070476

There you can find the most comprehensive explanation for negative resistance oscillators.

Unfortunately this concept doesn't make always a circuit to oscillate, which basically is the most important (and first thing that have to get) in oscillator design.

In my opinion is important in oscillator design to go deep in theory for: low phase noise, high frequency stability, low spurious emissions, but NOT for starting the oscillation.

I will post if get some results. Want to share something: I found few references to Alechno’s virtual ground circuit transformation technique, here is some link to mwrf.com in this topic: https://www.edaboard.com/thread10100.html but it seems that article does not exists online anymore. But i found some interesting article by Alechno: http://cp.literature.agilent.com/lit...989-9274EN.pdf

I have a question regarding Rload=-Rout/3 rule of thumb. For example "RF Circuit Design Theory and Applications" (Reinhold Ludwig, Gene Bogdanow): it is said than Rin becomes less negative with increasing output power, when oscillator start ups.
I am uncertain about some details.
For example, with 1-port negative resistance device such as gunn diode, it is pretty obvious:
we calculate Zload as Zload=-Zoutput. Then make newRload=Rload/3.

But for two-port device (BJT, FET) i am not so sure.
As we choose Rload=-Rout/3, should not we recalculate Ginput based on that new Gload?
I read many papers on negative resistance oscillators, and there always some uncertainity about what is called LOAD, what is SOURCE, what is Termination. Sometimes Gload is resonator, and oscillator is "loaded" with resonator. Sometimes resonator is termination, so it is "terminated" with resonator.

For example:

http://course.ee.ust.hk/elec518/lect9.pdf
Example 11-9
They choose real part of Zload=-Rin/3
Zload is at source pin of FET (common gate configuration)

and example in the boog "RF Circuit Design..." i mentioned before:
Example 10-5
They choose real part of Zload=-Rout/3 (actually a little smaller)
Zload is at drain pin of FET!

Both configurations are the same - commong gate FET oscillator. But in first case (variable names as in second book) Zinput is corrected. Is it arbitrary choosen which of termination corrected with this rule of thumb?

Which one to use, Rload=-Rout/3 or Rsource=-Rin/3?