CML Buffer optimum current consumption

Hi all,

I would like to ask you two questions.

1) If the the pull-up resistor is 50 Ohm, what conditions set the bias current (current tail) of the differential pair?
I know that ISS*50 Ohm should be < Vth of the differential pair for keeping the diff. pair in saturation.
So, if I do not choose the maximum current (i.e:Vth/50 Ohm) but I rather select less current (in order to save power consumption), this would be a problem for the termination load (which is also 50 Ohm, terminates to a network analyzer)

The cml buffer is on-chip design. The input frequency is 2GHz.


2) The diff. input signal is a rail2rail voltage swing. This transient signals are coming from CMOS inveters. Is that a problem for the functionality of the diff. pair? Ideally we would like something less (ie:Vin_diff> sqrt(2)*Vov but close to that value)

Let me know if something is not clear.

Thanks

If the outputs act truly like current sources (steered,
but high DC impedance) then amplitude does not affect
Zline / Zterm, only the noise margin of the next stage.

Bang-bang drive levels may make it impossible to get
saturated operation unless the load bias voltage is
above Vdd.

You might have a resistor tail or a current mirror tail
to set bias. In the former case the set-current depends
on input drive level.

You might like a replica bias scheme which forces an
equivalent, but not in signal path, CML stage's output
across termination to be a particular amplitude, and
use that master bias point to run the active gates too.
If you want to use inverters (and you generally will)
consider making a local supply for the closest-in ones
that limits overdrive (or, in the case of a resistor tail,
the inverter VOH -is- the bias point for the diff pair).

Hi dick_freebird,

thanks for your reply. I appreciate your answer.

Yes, my bias scheme is a current mirror.

What do you mean by saying that I can use a replica bias scheme which forces an equivalent CML stage's output
across termination to be a particular amplitude? Can you give an example? Or a paper if you know..

In general, I know what is a replica bias circuit. Like the one that we are using sometimes in charge pumps circuits. (PLL)


Can I create a local power supplies ( for the CMOS inverters) without using the resistive divider of LDO?

IN the event, I leave the rail2rail input voltage swing equal to vdd, it's not a big issue.. Right?

Thanks in advance

If you have rail-rail gate swing then your Vds will be
close to (Vgs-VT) and saturation region operation will
not be the case (borderline at best). If this is OK
(and it may be, because the master current source
will be in saturation) then fine.

If you have a voltage reference that can be "telegraphed"
to VDD-Vref, scaled, then you can put a cheesy op amp
to that and a half-buffer ("on") and feed the bias rail for
the buffer (and the live gates) from the op amp at null.
Presuming that the termination tail is the same VDD.