phase noise conversion
Like for example if the phase noise is 118 @ 10 MHz what will it be at 1 MHz?
any reference provided for a better understanding would be highly appreciated.
You can't, because that also depends on PLL design.
How the design is related to Phase noise? Can you please explain. In some references, I have seen that phase noise is calculated at 1 MHz offset but in some other papers it is calculated at 10 MHz. So can't we convert it to 1 MHz for those who have calculated it at 10 MHz? what is the difference?
See page.30-31 of http://cds.linear.com/docs/en/datasheet/6948fa.pdf
Also see https://www.edaboard.com/showthread.php?t=351341
since MOST pll control circuits have no effect beyond say 100 KHz....the phase noise of the system will roughly be the free running phase noise of the oscillator. And most oscillators will have about 20 dB more phase noise at 1 MHz than at 10 MHz, although this is only a "rule of thumb". Phase noise far from the carrier decreases 20 dB/decade until you get near the KTBF noise floor of the world.
Note this is NOT true if you pass the oscillator thru a digital divider gate before its output, as digital gates have a kind of FLAT noise floor far from the carrier.
From umberabbas previous question, I understand that this is for comparing different 60GHZ MMIC oscillator topologies. The 20dB/decade is a reasonable rule of thumb, but not accurate enough here in my opinion. Example below, where PLL bandwidth is around 1MHz (Nils Pohl et al, Digital Object Identifier 10.1109/TMTT.2011.2180398)
What is the main reason that some of the phase noise is measured at 10 MHz offset while others calculated it at 1 MHz? Does it solely depends upon the PLL/VCO design or are their other parameters that need to be considered for the phase noise to be measured at 10 MHz not 1 MHz?
It counts on the system design, such as modulation scheme.
For example, if the wireless is QPSK, then phase noise at 1K is very important. Even than 10K and 100K.
But if it's 64QAM, then 10K and 100K is sensitive, you can ignore 1K and 1M.
In radar, 10Hz and 100Hz is critical.
But in mmwave, 1M , maybe 10M is critical.
It's depend on your system. And you can simulate to get the phase noise requirement, but it need weeks for simualting the system.
well, i am looking at that graph and the phase noise at 10 MHz is about 20 db worse than at 1 MHz. LOL
Are there any other simulators than cadence for VCO design specially for varactors?
I like ADSimPLL, a free SW from AD.
It has many options for PLL design. But I don't know if it have VCO design with varactors.
Can we design varactors separately like in some other simulation tool?