How to create RF integrated circuit? From project to wafer and production.

1. What software is used?
2. How technology is selected? For example, if design contains 4-push oscillator with 10GHz output, would 2.4GHz process be enough?
3. How S-parameters are obtained? Through simulation? As i understand there may be some "standard" FET transistor, and it is used everywhere in the design.
4. How prototypes are made?
5. How much money is required for full setup one working place: PC+some design/simulation software+maybe some libraries for software+30 different prototypes on wafers. S10000 or maybe more?

1-Depends on what type of RFIC is considered.Cadence ADE,Keysight ADS,AWR Microwave Office are mainframes.But it depends mostly on what type of RFIC ? Silicon based or III IV based MMIC ?
2-Again, what type of and what purpose for.. Commercial or Military ? High volume or low volume ? For instance. You cannot use every process for every purpose.While GCS is manufacturing a process for Low Noise Oscillators ( I have personally used it ) WIN manufactures a process for Wideband Amplifiers.Other one manufactures High Power etc.You cannot use TSMC's 45nm process in designing of Space Qualified components There are many constraints and considerations.
3-S-parameters are generally measured by foundry and given in model.PDK.But s-parameters are not enough.There is no such component "general purpose FET"
4-It's along road.Since you have chosen the right process, you have to sign an agreement with the foundry then you can send your GDS files to foundry to make them prototype.The foundry send them to slicer company then packager ...long road.
5-Depends on again what process and which foundry.. But I say one thing. A tape-out with III IV process starts from 250 K .
6-Let me give you an example.. Keysight's ADS demands 60K S for full license for each user per year. Imagine the cost of a tape-out.

For the 130nm SiGe technologies that I know, shared wafer (multi project wafer) prototyping starts at 2500? per mm2, delivery is 40 dices samples.

Sounds cheap, but the difficulty is in design and design-rule-clean layout. I'm supporting these guys with EM simulation, and their toolset and workflow is really different from what RF PCB designers are used to. Much closer to device physics and technology.