Self biased inverter design with large resistor connected across it
I am trying to understand a self biased inverter with a large resistor connected across it. Why is it used at the output stage of LC oscillator and how large should this resistance be and why?
Thank you
It is used at the output of an LC oscillator to obtain rail to rail outputs. The inverter is biased at a point == tripping point of the inverter which is a high gain point. The self biased inverter is preceded by a coupling capacitor that couples the RF signal to the input. The time constant of the RC must be much greater than the half period of your oscillator to prevent any (significant) droop at the output. The C cannot be too large as it will load your oscillator. The R cannot be too large as you will start having layout parasitics at the input which would then form a voltage divider with your input coupling capacitor. A tradeoff needs to be made.
Sir,
Is there any way i can decrease the phase noise without affecting the amplitude of the signal?
PN is all about the edge rate and so is amplitude, if you
are "gain starved" - may need more than one stage to
get squared rail-rail and fed-back single stage inverters
don't have the greatest voltage gain (low Rout, sub-peak
gm). It could be that you'd be better off with one more
common-source gain stage and a capacitor-blocked
connection to the ->digital buffer chain (you will impose
less loading, one gate vs two, and perhaps enjoy a better
Rout (one drain and one load, separately optimizable, vs
a pair of low-Z drains).
Back when I used the coupled inverter stage, the phase noise of the coupled stage was quiet insignificant compared to that of the oscillator devices. Phase noise is always more impacted by noise of devices which form part of the feedback network (in this case the two transistors of the cross coupled LC oscillator).
Yes. The noise is from feedback network itself. When i try to increase the amplitude of the output, the phase noise is affected and vice versa.