hfss cap
The model of inter-digited capacitor I got from HFSS had a suspicious high value (190f and I was expecting 110f)
So i build a very simple test case: 2 plates of 10um*10um separated by 1um of oxyde (Er=3.9).
Everything is inside a vacuum box. I use lumped ports and driven terminal solution type.
If you apply the formula of the planar capacitor, you expect something around 3.45ff
I got 6ff from HFSS!
My extraction is at 10GHz to I expect HFSS to have problem with small geometries at this freq, but increasing the freq doesn't help so much...
Am I doing something stupid?
Please help, this test case makes me mad!
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I think I got part of the explanation...
The size of my cap is very small compared to the lambda, so the automatic meshing doesn't work really well here.... With 2 thin plates, HFSS generates "Failed to solve due to lack of precision"
I was using previously a big second plate, because I was trying to represent something over the substrate.
The problem is how can I solve this very simple case with enough precision? And will it work for more complex structures? If I can generate a small mesh manually, I will not be able to use It to model my 6 metal stacked (serial/parallel) inductor? I don't have 100Gb of memory available for that!
NB. I use Zo=1000 to avoid having S11=0.000000....
Somebody uses HFSS to extract metal-metal cap?
Any ideay?
Many thanks,
Eric
Eric -
I believe that the root cause of the discrepancy of your simulation results and analytical model (of parallel plate capacitor) is EDGE effects, or fringing, or periphery, capacitance. For the geometry you are using (10x10um plates with 1 um separation), the difference you are quoting is comparable with my estimates:
assuming that fringing/periphery capacitance is equivalent to adding an area to the plates by oversizing them by the spacing between the plates (1.0 um), you get an additional area of 4x10=40 um2 on top of 100 um2 - that is ~40% increase (assuming there is 3.9 epsilon everywhere).
You did not specify the thickness of the metal (thicker metals would increase fringing capacitance), and I am not sure if you really set epsilon=1 outside the capacitor - so there is no point to make more accurate estimates.
Practical suggestion - increase the size of the plates to 1000x1000 um (I hope HFSS would not choke at that), so that the edge effect becomes very small, then compare HFSS results with analytical model. Any discrepancy higher than ~1% should be then attributes either to inaccuracy in HFSS simulations (mesh effects etc.), or incorrect setting of your simulations in HFSS.
I did not have a direct experience with HFSS for MIM/MOM cap simulations, but some of my partners/customers have done so. HFSS builds a huge 3D mesh, requires very long simulation time (~1day per simulation run with frequency sweep), and provides relatively accurate values for capacitance and RF characteristics (resonant frequency, quality factor, etc.).
I am using a random walk based capacitance extraction, which is a rigorous field solver, it provides all required parameters (capacitance between the plates, capacitance to ground, capacitances to neighboring nets, quality factor, resonant frequency) with very short simulation times (~few minutes - for MIM/MOM capacitor of any size and with any metal interconnect environment). It reads in standard files (GDS layouts (or DFII or CCI/SVDB databases), technology files in any of the standard formats (itf, proc, ircx, ict - with all the advanced manufacturing effects taken into account), etc.), so that simulation setup is very simple and fast.
Max
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Thanks for your answer Max.
You're right for the fringing effect, but I already thought to it. Epsilon is 1 around the cap and I also tried with bigger sizes without sucess...
I know HFSS is not the best candidate for cap extraction, but my goal is to extract inductors, and I was investigating a problem of accuracy. My inductor uses many metal traces in top of each other (in serial), so a correct capacitance extraction is mandatory for me.
Thanks for the help,
Eric
Did you try to extract at lower frequencies (to make sure there is no parasitic series inductance effect that will show up as an increase in effective capacitance as you approach resonant frequency)?
I did...
Nb the resonnance frequeny is far away...
Eric
Well, if all plausible root causes are excluded, I would contact Ansoft's technical support for help...
Did somebody had a look at my test case?
Many thanks
Eric
Why had you used "-1/(2*pi()*freq*im(Zt(plate1_T1,plate1_T1)))*1e15", instead of "-1/(2*pi*freq*im(Zt(plate1_T1,plate1_T1)))*1e15" as the output? I find there some different between them.
At the same time, the lump port plane, which is one kinde of boundary condition, may also affect the result. This lump port is hard to coincide with the true field between plates. But I have no idea how to improve it.
pi() is a bad practice from Excel... I don't think It will affect the result, but I will try.
You're right with the lumped port...
Thanks for your help
Eric
Hi Timof,
I'm interested in knowing more about "random walk based capacitance extraction". Can you please give references of article, pdf files or presentations about it ?
Which software do you use in which the method is implemented ?
Thanks for your answer,
Xof
Just make a search on "random walk capacitance" (without quotes) to get a bunch of references. You can also search IEEE or AIP web sites for more references.
I am using F3D from Silicon Frontline (Silicon Frontline Guaranteed Accurate Parasitic Extraction and Analysis ? Silicon Frontline).
Interesting !
Do you have an idea of the cost for a licence of this software ?
Thnaks in advance.
The list price is in the range typical for EDA/CAD tools, and the actual price is customer specific.
I suggest that you contact Silicon Frontline ("Contact Us" page if you need more detailed info).