on die capacitance extraction

Hi All, I would like to seek expertise on die capacitance extraction area.

My understanding about on die parasitic capacitance is it includes metal grid capacitance as well as device capacitance from transistor. (pls correct me if i am wrong)

Question:-
for the metal grid capacitance, it can be categorised into coplanar and adjacent layer as long as it has the power and ground overlapped structure. Is the metal grid capacitance exist only toward the next layer (for instance metal3 to metal2 capacitance) or toward other layers that far away from the current layer (metal3 to substrate layer)? if yes, is the n-doping and p-doping of substrate impact the total intrinsic capacitance obtained?

thanks in advance.