PIN Diode representation in CST

Hi, im doing freq reconfigurable antenna. So, im using PIN diode and lumped element.. How can i represent a PIn diode and lumped elements in cst? Any additional setting or simulation setup?
Thankss

you can use hardwire connection for the diodes which are ON and no connection for the diodes which are OFF

Added after 4 minutes:

i.e. for each reconfigurable state you should replace diodes with ideal connection.

If you want to be more precise, you can use the equivalent circuit model for the ON and OFF state of the diodes

yes;I m agree with you amihomo

The losses and isolation of PIN diodes have a significant effect on the simulation, so if you want accurate simulations you must include the diode model.
Including a circuital model in full-wave simulations is not straightforward. One effective way is to model the diode as a RLC boundary.
Actually, I've tried them (also for modelling PIN diodes) in HFSS and they work well. I don't know if it can be done in CST.
One tip: made the boundary as small as possible.

A different way consists on modelling the PIN diode is to locate a port instead and perform a post-processing loading the port with the circuit model.

In HFSS you can use Lumped RLC boundary condition to simulate PIN diodes or varactors .

i am trying to model pin diode in hfss. If you have that model or any tutorial please send it to my mail. please,it is very helpful to me. my mail id: yuvasindhu.m@gmail.com

Hi everybody, for PIN Diode simulation in CST you can applie two method:
1) you can simulate the PIN diode by its equivalent circuit (RLC)
2) Or you can simulate the PIN Diode like this: In the OFF mode, the PIN Diode is removed from the simulation and the antenna should be simulated with a complete slot. When the PIN is ON, it is modeled as a metal tape.
You can see this article, it will be very usefull for you:http://onlinelibrary.wiley.com/doi/1...mop.27649/full
good luck and welcome for any question.

Depending on the application, you should at least leave the pin diode capacitance (off-state) and the on resistance (on-state) in the simulation.

When using as segment ("metal tape") during on state simulation, you may decrease the conductivity to increase the resistance of that segment.

When simulating the off-state, you can add some segments so that the capacitance increases (to simulate the pin diode capacitance). you may need a seperate simulation to find out the conductivity (on-state) and length of the air gap (off-state).

The link you provided is very useful, however, can you provide more details on how to draw its equivalent model in CST? and the steps..
I am trying first with a BAR 63 PIN diode.