Effect of Increase/decrease of rise/fall time of input to a Invertor

Hi

I am glad to know the effect on output of the Buffer which is made by cascading two invertor ciruits with Increase/decrease of rise/fall time of input to the first invertor Invertor.

Logic IC's are made to change state of their output as quickly as possible. It becomes more important at fast data rates.

From my experiments it didn't matter how slowly or quickly the input crosses the threshold between lo and hi. I found I was unable to obtain a middle output.

This assumes the output is not loading the IC supply pins so much as to cause peculiar influence back at the input.

Also it assumes no circuitry is installed to loop the output back to the input.

I tried out a circuit I saw, that made an analog application (amplifier) out of 3 inverters (digital). It was nothing more than a high ohm resistor. (With a lesser ohm value installed at the input). The last inverter produced analog waveforms riding a DC component equal to supply/2.