[Moved]: roundrobin using verilog hdl

i had a problem in roundrobin when two requests are granted .when there is only one request it is allocating the grant properly but when there are two requests it is allocating grant only for one state but i want it to allocate for two states?.how can i do that any suggestions

Maybe each device needs to monitor system communications, and wait until it is idle, then send its request?

Or... In computer networking, there is an extra wire, which is used by remote devices to notify the central device that they require attention. Then a device waits until it gets a 'go ahead' signal (on another wire). This method adds to complexity, however it is better than having simultaneous requests cause confusion.

Eiter you change your state machine to be capable of processing two (or more) requests in parallel, or you may store the pending requests in a DFF stage, and process them one after another (similar like handling concurrent IRQs in μC).

how to change the state machine.can you please explain detail how can i allocate two requests

It's difficult to explain without havin an idea about your design.
Please show us your current design of the HDL statemachine, and the inputs it cannot handle.

If there exists the possibility of conflicting requests from different sources, you should consider implementing in a higher layer, a two way communication protocol on which receiver emits a confirmation back to senders informing the ID/address from the one which was acknowledged. Anyway, I agree that the question, as posed, is too vague.