ads momentum substrate

In the substrate modify option of momentum, In the metallization layes modify,
Does anyone can give me a clear explaination about the overlap precedence.

Hi
You can assign two or more different matirials on the same layer
Matirial with more precedence number will cover less precedence matirial
It is useful you want to model resistor for ex.

Thank you for your explaination. But I still don't understand how can I assign two materials into one layer, and one more question: how do the Via's overlap precedence affects the simulation results? Because when I simulation in the momentum If I change the via's overlap precedence, the simulation results changes too! I'm sure the condition that two materials in one layer is not exist in my simulation setup. Thank you for your help.

Hi
Chouse metal layer in substrate setup for ex. cond
Click strip

Chouse metal layer in substrate setup for ex. cond2
Click strip

You will have cond and cond2 on the same bondary betweem dielectric substrate layer

Precedence sets which metal will be assumed in the simulation when (for ex) cond2 rectagle cover cond rectagle

The logic for via the same

Regards

Hi
Thank you for your particular explaination. Now I understand hoiw to set two materials into one layer. But in my simulation there is no layer containing two materials.
the layer setup is like this

air
metal1 overlap precedence=1 for ex
dielectric1 via
metal2 overlap precedence=2 for ex
dielectric

the overlap precedence setting of the via is gray, but will change by the click sequence like this:
If I click metal2 then click via, the via's overlap precedence is 2
If I click metal1 then click via, the via's overlap precedence is 1

The momentum results of the two setting is different, which I don't understand. How did the overlap precedence change the simulation results.
Did you ever meet this in your simulation? Thank you for help.

Best regards

Hi
I think You should not use metal1 like via if metal1 is strip.
Use different metal layers for via and for strip

Hi , via is dedined in a substrate layer, not in the metal layer. the via and metal1 are not in the same layer.

Hello
e-mail (or upload) me your design, Please
I want to see what this realy