ADC的veriloga代码求解
时间：10-02
整理：3721RD
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各位大神，小弟最近新接触veriloga代码，ADC也只是了解其基本的原理与一些概念，下面这段代码我看不出怎么实现ADC的，我也认真看了，还是入门比较吃力吧，求帮助
The following example, an N-bit analog to digital converter, demonstrates the ability of
the transition function to handle vectors.
module a2d(in, clk, out) ;
parameter bits=8, fullscale=1.0, delay=0, ttime=10n ;
input in, clk ;
output [0:bits-1] out ;
electrical in, clk, out ;
real sample, thresh ;
integer result[0:bits-1], i ;
analog begin
@(cross(V(clk)-2.5, +1) begin
sample = V(in) ;
thresh = full_scale/2.0 ;
for(i=bits-1; i>=0; i=i-1) begin
if (sample > thresh) begin
result[i] = 1 ;
sample = sample - thresh ;
end
else result[i] = 0 ;
sample = 2.0*sample ;
end
end
V(out) <+ transition(result,delay,ttime) ;
end
endmodule
The following example, an N-bit analog to digital converter, demonstrates the ability of
the transition function to handle vectors.
module a2d(in, clk, out) ;
parameter bits=8, fullscale=1.0, delay=0, ttime=10n ;
input in, clk ;
output [0:bits-1] out ;
electrical in, clk, out ;
real sample, thresh ;
integer result[0:bits-1], i ;
analog begin
@(cross(V(clk)-2.5, +1) begin
sample = V(in) ;
thresh = full_scale/2.0 ;
for(i=bits-1; i>=0; i=i-1) begin
if (sample > thresh) begin
result[i] = 1 ;
sample = sample - thresh ;
end
else result[i] = 0 ;
sample = 2.0*sample ;
end
end
V(out) <+ transition(result,delay,ttime) ;
end
endmodule
自己顶一下，坐等大神帮助
这段程序有问题吧，我怎么感觉sample = sample - thresh ;应该改为sample = 2*（sample - thresh ）
我的感觉是在这句
if (sample > thresh) begin
result[i] = 1 ;
sample = sample - thresh ;
后面加个thresh=thresh/2。然后把
else result[i] = 0 ;
sample = 2.0*sample 乘以2这句去掉，再加上thresh=thresh/2；跟你说的那个乘以2有点相似。感觉按你说的改也和我说的改效果一样，但是我感觉我这么改是不是更直观点呢，我自己的想法，求交流指导