求助：关于vcs跑uvm，遇上timeout的问题
最近在学UVM，按照书上的例子弄了个简单的跑一下，结果使用vcs的时候，每次都是到9200ns的时候自动停止了，而使用irun跑的时候不会这样，有没有人遇到过这种问题呢?我实在是丈二和尚摸不着头脑呀。
VCS的信息：
UVM_INFO：@ 0：reporter [RNTST] Running test my_case0...
UVM_WARNING @ 0: uvm_test_top.env [UVM_DEPRECATED] build()/build_phase() has been called explicitly,outside of the phasing system. This usage of build is deprecated and may lead to unexpected behavior.
now trans num is1
hahaha ........ Compare SUCCESSFULLY
UVM_ERROR /opt1/eda_tools/synopsys/vcsmx_vF/etc/uvm-1.1/base/uvm_phase.svh(1203) @9200:reporter [PH_TIMEOUT] Default phase timeout of 9200 hit. All processes are waiting,indicationg a probable testbench issue.Phase 'main' ready to end
UVM_WARNING @ 9200 : main [OBJTN_CLEAR] Object 'uvm.uvm_sched.main' cleared objection counts for main
而用nc的irun跑出的信息如下：
UVM_INFO @ 0: reporter [RNTST] Running test my_case0...
UVM_WARNING @ 0: uvm_test_top.env [UVM_DEPRECATED] build()/build_phase() has been called explicitly,outside of the phasing system .This usage of build is deprecated and may lead to unexpected behavior.
now trans num is1
hahaha ........ Compare SUCCESSFULLY
now trans num is2
hahaha ........ Compare SUCCESSFULLY
now trans num is3
hahaha ........ Compare SUCCESSFULLY
now trans num is4
hahaha ........ Compare SUCCESSFULLY
now trans num is5
hahaha ........ Compare SUCCESSFULLY
now trans num is6
hahaha ........ Compare SUCCESSFULLY
now trans num is7
hahaha ........ Compare SUCCESSFULLY
now trans num is8
hahaha ........ Compare SUCCESSFULLY
now trans num is9
hahaha ........ Compare SUCCESSFULLY
now trans num is10
hahaha ........ Compare SUCCESSFULLY
.....
.....
Simulation completed via $finish(1) at time 141290 NS + 79
哦。不好意思，刚才找到了暂时解决的办法，在执行simv时候加上 +UVM_TIMEOUT=1000000就能全跑出来了。可是各位有没有更好的办法呀，这还是一个很小的仿真程序，要是大点的都不知道要设多大的TIMEOUT了。
这个应该和软件的设置文件里面的timeout默认值有关系，看你加的参数就知道了，不过这两个软件的设置文件是什么我不太清楚，你应该找到以后把里面的timeout值修改到目前这个10000000，应该就能一劳永逸了。
兄弟，你肯定是某个phase没有drop，所以导致超时
default应该是9200s,已经很长了，你怎么是9200ns?
小编的问题如何解决的?解决了吗?
遇到了同样的问题，讨论一下哈。
我是在VCS调用verdi的时候 编译能过，但是仿真时报这个错误
你的timescale没设,
VCS-timescale=1ns/1ps ....
did it remained suolveless?
我这边出现的问题正好相反，仿真时间直接跑不动，在第0 ns的时候就finish掉了，不清楚为什么，log文件如下：
ncsim> run
----------------------------------------------------------------
CDNS-UVM-1.1d (13.20-p002)
(C) 2007-2013 Mentor Graphics Corporation
(C) 2007-2013 Cadence Design Systems, Inc.
(C) 2006-2013 Synopsys, Inc.
(C) 2011-2013 Cypress Semiconductor Corp.
----------------------------------------------------------------
UVM_INFO @ 0: reporter [RNTST] Running test my_test...
UVM_WARNING @ 0.0 ns: uvm_test_top.env [UVM_DEPRECATED] build()/build_phase() has been called explicitly, outside of the phasing system. This usage of build is deprecated and may lead to unexpected behavior.
--- UVM Report catcher Summary ---
Number of demoted UVM_FATAL reports:0
Number of demoted UVM_ERROR reports:0
Number of demoted UVM_WARNING reports:0
Number of caught UVM_FATAL reports:0
Number of caught UVM_ERROR reports:0
Number of caught UVM_WARNING reports :0
--- UVM Report Summary ---
** Report counts by severity
UVM_INFO :1
UVM_WARNING :1
UVM_ERROR :0
UVM_FATAL :0
** Report counts by id
[RNTST]1
[UVM_DEPRECATED]1
Simulation complete via $finish(1) at time 0 FS + 179
/opt/cadence/INCISIV132/tools/methodology/UVM/CDNS-1.1d/sv/src/base/uvm_root.svh:457$finish;
ncsim> exit
请问有见过这种问题吗?
我这里也解决了，sequence中没有start phase，找了半天才找到demo中的这个问题
小编我想问下，什么原因会造成验证的时候会出现timeout，谢谢了
这个问题一直不清楚。
加上timescale选项应该就可以，
9楼正解，牛逼，没有设置timescale,我一直以为timescale要在sv文件里面设置，老是出错，原来可以还可以在makefile中设置
9楼正解，牛逼，我一直以为timescale需要在sv文件中设置，原来可以直接在makefile中设置，赞
虽然我遇到的不是这个问题，但也来学习下
为什么跟timescale有关系呢?