UVM 中对reg_model进行read操作不成功

task my_model::main_phase(uvm_phase phase);
my_transaction tr;
my_transaction new_tr;
uvm_status_e status;
uvm_reg_data_t value;
super.main_phase(phase);
p_rm.invert.read(status, value, UVM_FRONTDOOR);
p_rm.invert.write(status, 1, UVM_FRONTDOOR);//这里进行写操作
p_rm.invert.read(status, value, UVM_FRONTDOOR);//这里进行读操作
while(1) begin
port.get(tr);
new_tr = new("new_tr");
new_tr.copy(tr);
//`uvm_info("my_model", "get one transaction, copy and print it:", UVM_LOW)
//new_tr.print();
`uvm_info("my_model",$sformatf("0000: invert value is : %0d",value),UVM_LOW)//这里value的值应该为1
if(value)
invert_tr(new_tr);
ap.write(new_tr);
end
endtask

但是运行结果显示 value的值还是为0，这里对reg_model的操作都是在reference_model中进行的

请教大神 ，这是哪里调用的不对么?

已搞定，是因为在bus_driver的代码中读操作之后，立即将vif.bus_rd_data 赋给了 tr.rdata，而此时
需要一定的时间延时
task bus_driver::drive_one_pkt(bus_transaction tr);
`uvm_info("bus_driver","begin to drive one pkt",UVM_LOW);
repeat(1) @(posedge vif.clk);
vif.bus_cmd_valid <= 1'b1;
vif.bus_op <= ((tr.bus_op == BUS_RD)?0:1);
vif.bus_addr <= tr.addr;
vif.bus_wr_data <= ((tr.bus_op == BUS_RD)?0:tr.wr_data);
@(posedge vif.clk);
vif.bus_cmd_valid <= 1'b0;
vif.bus_op <= 1'b0;
vif.bus_addr <= 16'b0;
vif.bus_wr_data <= 16'b0;

#1;//加上这一个延时即可
if(tr.bus_op == BUS_RD) begin
tr.rd_data = vif.bus_rd_data;
end
`uvm_info("DEBUG",$sformatf("bus_op = %0d, tr.rd_data = %h:%h",tr.bus_op,tr.rd_data,vif.bus_rd_data),UVM_LOW)
`uvm_info("bus_driver","end drive one pkt",UVM_LOW);
endtask