后仿真，sdf中的timing check 没效果，求指点

*Novas* End of traversing the scope(tb_chip)
driver initialization ok！
Doing SDF annotation ...... Done
Test begin！
*******************************************************************
the testname is 00000003
*******************************************************************
theHH BTA_END is163122300

"/project/StdCell_lib/ush130h32sc_2013q2_v3r3/Verilog/ush130h32sc.v", 4437: Timing violation in tb_chip.U_impro.U_ddr3_top.U_tx_phy.data_out_n_reg
$setuphold( posedge CK &&& (flag == 1'b1):177498792, posedge D:177498700, limits: (100,50) );

"/project/StdCell_lib/ush130h32sc_2013q2_v3r3/Verilog/ush130h32sc.v", 4438: Timing violation in tb_chip.U_impro.U_ddr3_top.U_tx_phy.cmd_out_n_reg
$setuphold( posedge CK &&& (flag == 1'b1):177498792, negedge D:177498700, limits: (100,50) );

"/project/StdCell_lib/ush130h32sc_2013q2_v3r3/Verilog/ush130h32sc.v", 4437: Timing violation in tb_chip.U_impro_chip.U_ddr3_top.U_tx_phy.div_en_cnt_reg_1_
$setuphold( posedge CK &&& (flag == 1'b1):177498792, posedge D:177498700, limits: (100,50) );
以上是simulation 中的warning
----------------------------------------------------------------------------------------------------------------
(CELL
(CELLTYPE"DFFRDL")
(INSTANCEU_tx__phy/data_out_n_reg)
(DELAY
(ABSOLUTE
(IOPATH RB Q() (0.997::0.997))
(IOPATH RB QB(0.884::0.884) ())
(IOPATH (posedge CK) Q(1.229::1.229) (0.848::0.848))
(IOPATH (posedge CK) QB(0.736::0.736) (1.123::1.123))
)
)
(TIMINGCHECK
(WIDTH (negedge RB) (::1.687))
(WIDTH (posedge CK) (::0.375))
(WIDTH (negedge CK) (::0.544))
(SETUPHOLD (posedge D) (posedge CK) (::0.271) (::-0.232))
(SETUPHOLD (negedge D) (posedge CK) (::0.208) (::-0.038))
(RECREM (posedge RB) (posedge CK) (::0.315) (::-0.278))
)
)
这个是sdf 中对应的Timingcheck 部分。

我从simulation的warning （红色部分）中觉得sdf的timing check 没效果，好像有的是仿真库文件中的值 ，但是编译过程sdf 反标的log中没有看到error， 也显示了反标结束， sdf 反标的warning中没有关于上面几个寄存器的内容。 我第一次搭建后仿真环境，不知道有什么地方出了问题，希望各位大神指点一下
反标过程中的warning，基本上是 negtive value cannot handle by the switch -negdelay

(CELL
(CELLTYPE "DFFRDL")
(INSTANCE U_tx_lp_phy/data_out_n_reg)
(DELAY
(ABSOLUTE
(IOPATH CK Q (1.153::1.153) (0.773::0.773))
(IOPATH CK QB (0.674::0.674) (1.061::1.061))
(IOPATH RB Q () (1.024::1.035))
(IOPATH RB QB (0.924::0.935) ())
)
)
(TIMINGCHECK
(WIDTH (negedge CK) (0.559::0.559))
(WIDTH (posedge CK) (0.342::0.342))
(WIDTH (negedge RB) (1.875::1.935))
(SETUP (posedge D) (posedge CK) (0.273::0.361))
(SETUP (negedge D) (posedge CK) (0.260::0.296))
(SETUP (posedge RB) (posedge CK) (0.391::0.401))
(HOLD (posedge D) (posedge CK) (-0.272::-0.228))
(HOLD (negedge D) (posedge CK) (-0.114::-0.084))
(HOLD (posedge RB) (posedge CK) (-0.359::-0.351))
)
)
这是我重新提的一个sdf ，问题依旧

仿真中的timing violation，可以检查一下是不是由false path造成的，如果是，加入仿真的notiming check列表即可。sdf反标能不能标上可以看下特定寄存器的延时，对比sdf文件的timing信息。

if this path is actually crossing two clock domains, we should really care about this timing violation. you will probably miss this issue using no-timing check, right?

“”反标过程中的warning，基本上是 negtive value cannot handle by the switch -negdelay“”这种warning不需要关注吗?