急问。VCS怎么加载SDF文件

可能是sdf版本的问题

多谢回复。现在好了。我在test pattern里面，直接加戴$sdf_annotate();
但这个时候由于sdf的路径是到设计的顶层。而我的gate_sim顶层是到test bench为止。是不是需要人为的修改timing arc的路径?

$sdf_annotate();
这里需要指定你要标到哪个module 上面去

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多谢。有个问题。我的test bench里面例化了两个design.这种情况该怎么标。比如我的design是aaa.
test bench里面有两个，hierachy分别是tb/aaa_0和tb/aaa_1。这种情况怎么弄?谢谢

这种情况我还没有见到过，也不清楚怎么弄。看看能否指定两个module

Separate Annotations
This example shows separate annotations to distinct portions of a design hierarchy. There is
no configuration file specification, so the SDF Annotator uses the defaults.
module top;
•••
cpu m1(i1,i2,i3,o1,o2,o3);
fpu m2 (i4,o1,o3,i2,o4,o5,o6);
dma m3(o1,o4,i5,i6,i2);
// perform annotation
initial
begin
$sdf_annotate("cpu.sdf",m1,,"cpu.log");
$sdf_annotate("fpu.sdf",m2,,"fpu.log");
$sdf_annotate("dma.sdf",m3,,"dma.log");
end
// stimulus and response-checking
•••
endmodule
Annotation with Arrays of Instances
This example shows arrays of instance in a design hierarchy. There is no configuration file
specification, so the SDF Annotator uses the defaults.
module top;
•••
cpu ar[1](i1,i2,i3,o1,o2,o3);
fpu ar[2](i4,o1,o3,i2,o4,o5,o6);
dma ar[3](o1,o4,i5,i6,i2);
// perform annotation
initial
begin
$sdf_annotate("cpu.sdf",ar[1],,"cpu.log");
$sdf_annotate("fpu.sdf",ar[2],,"fpu.log");
$sdf_annotate("dma.sdf",ar[3],,"dma.log");
end
// stimulus and response-checking
•••
endmodule

Separate Annotations