Error: Failed to find 'PLL_LOCKG' in hierarchical name

今天在Modelsim仿真Xilinx设计的时候遇到了这样一个很奇怪的错误：

1. 
   
2. # Model Technology ModelSim SE vcom 6.5c Compiler 2009.08 Aug 27 2009
   
3. # -- Loading package standard
   
4. # -- Loading package std_logic_1164
   
5. # -- Loading package numeric_std
   
6. # -- Loading package vcomponents
   
7. # -- Compiling entity ii_clk_align
   
8. # -- Compiling architecture arch of ii_clk_align
   
9. # vsim -L work -L secureip -L simprims_ver -L uni9000_ver -L unimacro_ver -L unisims_ver -L unisim -L xilinxcorelib_ver -coverage -voptargs=\"+acc\" -pli novas.dll -suppress 3486 -t 1ps -vopt work.glbl work.tb_top
   
10. # ** Note: (vsim-3812) Design is being optimized...
    
11. # ** Note: (vsim-3865) Due to PLI being present, full design access is being specified.
    
12. # ** Error: C:/Xilinx/12.3/ISE_DS/ISE/verilog/src/unisims/PLL_ADV.v(1108): Failed to find 'PLL_LOCKG' in hierarchical name.
    
13. # Optimization failed
    
14. # Error loading design

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网上搜了一下也没什么解决方法，glbl.v也看了，也看了脚本，都没问题。后来用debussy看了一下，发现glbl里果然没有'PLL_LOCKG‘，原来这个glbl的顶层和glbl.v的内容不一样，很多xilinx的IP里面自己也是带glbl模块的。于是原因找到了：我在脚本里把glbl.v是放在第一个compile的，所以后来的IP里自带的glbl把glbl.v给覆盖了，导致找不到'PLL_LOCKG‘。
解决方法：把glbl.v放到source file complie list的最后一个。
IP里的glbl

1. 
   
2. `timescale1 ps / 1 ps
   
3. module glbl ();
   
4. parameter ROC_WIDTH = 100000;
   
5. parameter TOC_WIDTH = 0;
   
6. wire GSR;
   
7. wire GTS;
   
8. wire PRLD;
   
9. reg GSR_int;
   
10. reg GTS_int;
    
11. reg PRLD_int;
    
12. //--------JTAG Globals --------------
    
13. wire JTAG_TDO_GLBL;
    
14. wire JTAG_TCK_GLBL;
    
15. wire JTAG_TDI_GLBL;
    
16. wire JTAG_TMS_GLBL;
    
17. wire JTAG_TRST_GLBL;
    
18. reg JTAG_CAPTURE_GLBL;
    
19. reg JTAG_RESET_GLBL;
    
20. reg JTAG_SHIFT_GLBL;
    
21. reg JTAG_UPDATE_GLBL;
    
22. reg JTAG_SEL1_GLBL = 0;
    
23. reg JTAG_SEL2_GLBL = 0 ;
    
24. reg JTAG_SEL3_GLBL = 0;
    
25. reg JTAG_SEL4_GLBL = 0;
    
26. reg JTAG_USER_TDO1_GLBL = 1'bz;
    
27. reg JTAG_USER_TDO2_GLBL = 1'bz;
    
28. reg JTAG_USER_TDO3_GLBL = 1'bz;
    
29. reg JTAG_USER_TDO4_GLBL = 1'bz;
    
30. assign (weak1, weak0) GSR = GSR_int;
    
31. assign (weak1, weak0) GTS = GTS_int;
    
32. assign (weak1, weak0) PRLD = PRLD_int;
    
33. initial begin
    
34. GSR_int = 1'b1;
    
35. PRLD_int = 1'b1;
    
36. #(ROC_WIDTH)
    
37. GSR_int = 1'b0;
    
38. PRLD_int = 1'b0;
    
39. end
    
40. initial begin
    
41. GTS_int = 1'b1;
    
42. #(TOC_WIDTH)
    
43. GTS_int = 1'b0;
    
44. end
    
45. endmodule

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glbl.v

1. `timescale 1 ps / 1 ps
   
2. 
   
3. module glbl ();
   
4. 
   
5. parameter ROC_WIDTH = 100000;
   
6. parameter TOC_WIDTH = 0;
   
7. 
   
8. wire GSR;
   
9. wire GTS;
   
10. wire GWE;
    
11. wire PRLD;
    
12. tri1 p_up_tmp;
    
13. tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
    
14. 
    
15. reg GSR_int;
    
16. reg GTS_int;
    
17. reg PRLD_int;
    
18. 
    
19. //-------- JTAG Globals --------------
    
20. wire JTAG_TDO_GLBL;
    
21. wire JTAG_TCK_GLBL;
    
22. wire JTAG_TDI_GLBL;
    
23. wire JTAG_TMS_GLBL;
    
24. wire JTAG_TRST_GLBL;
    
25. 
    
26. reg JTAG_CAPTURE_GLBL;
    
27. reg JTAG_RESET_GLBL;
    
28. reg JTAG_SHIFT_GLBL;
    
29. reg JTAG_UPDATE_GLBL;
    
30. reg JTAG_RUNTEST_GLBL;
    
31. 
    
32. reg JTAG_SEL1_GLBL = 0;
    
33. reg JTAG_SEL2_GLBL = 0 ;
    
34. reg JTAG_SEL3_GLBL = 0;
    
35. reg JTAG_SEL4_GLBL = 0;
    
36. 
    
37. reg JTAG_USER_TDO1_GLBL = 1'bz;
    
38. reg JTAG_USER_TDO2_GLBL = 1'bz;
    
39. reg JTAG_USER_TDO3_GLBL = 1'bz;
    
40. reg JTAG_USER_TDO4_GLBL = 1'bz;
    
41. 
    
42. assign (weak1, weak0) GSR = GSR_int;
    
43. assign (weak1, weak0) GTS = GTS_int;
    
44. assign (weak1, weak0) PRLD = PRLD_int;
    
45. 
    
46. initial begin
    
47. GSR_int = 1'b1;
    
48. PRLD_int = 1'b1;
    
49. #(ROC_WIDTH)
    
50. GSR_int = 1'b0;
    
51. PRLD_int = 1'b0;
    
52. end
    
53. 
    
54. initial begin
    
55. GTS_int = 1'b1;
    
56. #(TOC_WIDTH)
    
57. GTS_int = 1'b0;
    
58. end
    
59. 
    
60. endmodule

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顺利解决，~