verilog中PLI中传参数和返回值
时间:10-02
整理:3721RD
点击:
近来想研究下verilog中pli的问题,
一个简单的打印可以成功实现,但是一个稍微复杂点,带有参数和返回值的应用就失败了,请高手指教
我的例子是
testbench:
`timescale 1ns/1ns
module tb;
reg [7:0] a, b;
reg [7:0] c;
initial begin
a = 1;
b = 2;
#9;
a = 3;
b = 5;
end
initial begin
$display(" a is %0h, b is %0h, c is %h", a, b, c);
#1;
$display(" a is %0h, b is %0h, c is %h", a, b, c);
$sum(a,b);
$hello;
#10;
$display(" a is %0h, b is %0h, c is %h", a, b, c);
end
endmodule
pli tab 文件
$sumcall=sumacc=rw:*
$hellocall=hello acc=rw:*
cpp 文件:
#include <stdio.h>
#include "acc_user.h"
/*
int sum (int a, int b)
{
int sum;
sum = a +b ;
}
*/
extern "C" {
void hello ()
{
printf ( "hello world!\n");
printf ( "it is cpp\n");
}
int sum (int a, int b)
{
int sum;
sum = a + b;
printf("a is %0d\n", a);
printf("b is %0d\n", b);
printf("sum is %0d\n", sum);
return sum;
}
}
仿真结果是
a is 1, b is 2, c is xx
a is 1, b is 2, c is xx
a is 0
b is 3
sum is 3
hello world!
it is cpp
a is 3, b is 5, c is xx
明显C没有拿到a,b的值。另外怎样返回一个值到verilog,
一个简单的打印可以成功实现,但是一个稍微复杂点,带有参数和返回值的应用就失败了,请高手指教
我的例子是
testbench:
`timescale 1ns/1ns
module tb;
reg [7:0] a, b;
reg [7:0] c;
initial begin
a = 1;
b = 2;
#9;
a = 3;
b = 5;
end
initial begin
$display(" a is %0h, b is %0h, c is %h", a, b, c);
#1;
$display(" a is %0h, b is %0h, c is %h", a, b, c);
$sum(a,b);
$hello;
#10;
$display(" a is %0h, b is %0h, c is %h", a, b, c);
end
endmodule
pli tab 文件
$sumcall=sumacc=rw:*
$hellocall=hello acc=rw:*
cpp 文件:
#include <stdio.h>
#include "acc_user.h"
/*
int sum (int a, int b)
{
int sum;
sum = a +b ;
}
*/
extern "C" {
void hello ()
{
printf ( "hello world!\n");
printf ( "it is cpp\n");
}
int sum (int a, int b)
{
int sum;
sum = a + b;
printf("a is %0d\n", a);
printf("b is %0d\n", b);
printf("sum is %0d\n", sum);
return sum;
}
}
仿真结果是
a is 1, b is 2, c is xx
a is 1, b is 2, c is xx
a is 0
b is 3
sum is 3
hello world!
it is cpp
a is 3, b is 5, c is xx
明显C没有拿到a,b的值。另外怎样返回一个值到verilog,
请大侠指点
最好能给出详细的code。
谢谢!
没有人知道吗?
这帖子沉了?
难道就没有做verilog的PLI开发的?
好象没有把sum值assign给C, 是不是要用: c=$sum(a,b);