关于systemverilog assertion中的空成功

发现dump出来的wave里每个cycle都显示一个空成功,很不爽.各位有没有什么办法去掉这些没用的.还有一问,为什么verdi里面如果加入 $fsdbDumpSVA;$fsdbDumpvars(0,top,"+all");后event变量却不能dump出来?

使用 -assert filter 可以将空成功去掉吧?
VCS User Guide原文：
-assert keyword_argument
filter
Blocks reporting of trivial implication successes. These happen
when an implication construct registers a success only because
the precondition (antecedent) portion is false (and so the
consequent portion is not checked). With this option, reporting
only shows successes in which the whole expression matched.