做pt的时候需要再次定义时钟吗？
你的sdc里不是应该有才对吗
读sdc文件时一直出错，要么就是找不到match的时钟要么就是找不到net。不知道为什么。
读入sdc出错的话，后面肯定会报错了，是什么错误，贴上来看看
Error: Nothing matched for net_list (SEL-005)
Warning: No net objects matched 'U4IM/u1/add_309/n13' (SEL-004)
Error: Nothing matched for nets (SEL-005)
Error: Nothing matched for net_list (SEL-005)
Warning: No net objects matched 'U4IM/u1/add_309/n14' (SEL-004)
Error: Nothing matched for nets (SEL-005)
Error: Nothing matched for objects (SEL-005)
Warning: No net objects matched 'U4IM/u1/add_309/n14' (SEL-004)
Error: Nothing matched for nets (SEL-005)
Error: Nothing matched for objects (SEL-005)
Warning: No net objects matched 'U4IM/u1/add_309/n14' (SEL-004)
Error: Nothing matched for nets (SEL-005)
Error: Nothing matched for net_list (SEL-005)
Warning: No net objects matched 'U4IM/u1/add_309/n14' (SEL-004)
Error: Nothing matched for nets (SEL-005)
Error: Nothing matched for net_list (SEL-005)
Warning: No net objects matched 'U4RE/u1/add_309/n13' (SEL-004)
Error: Nothing matched for nets (SEL-005)
Error: Nothing matched for objects (SEL-005)
Warning: No net objects matched 'U4RE/u1/add_309/n13' (SEL-004)
Error: Nothing matched for nets (SEL-005)
Error: Nothing matched for objects (SEL-005)
Warning: No net objects matched 'U4RE/u1/add_309/n13' (SEL-004)
Error: Nothing matched for nets (SEL-005)
Error: Nothing matched for net_list (SEL-005)
Warning: No net objects matched 'U4RE/u1/add_309/n13' (SEL-004)
Error: Nothing matched for nets (SEL-005)
Error: Nothing matched for clock_name (SEL-005)Warning: Nothing implicitly matched 'clkr_h' (SEL-003)
Error: Nothing matched for clock_name (SEL-005)
Warning: Nothing implicitly matched 'clkr_l' (SEL-003)
Error: Nothing matched for clock_name (SEL-005)
Warning: Nothing implicitly matched 'clkr_l' (SEL-003)
Error: Nothing matched for clock_name (SEL-005)
Warning: Nothing implicitly matched 'clkr_h' (SEL-003)
Error: Nothing matched for clock_name (SEL-005)
Warning: Nothing implicitly matched 'clkr_h' (SEL-003)
Error: Nothing matched for clock_name (SEL-005)
Warning: Nothing implicitly matched 'clkr_l' (SEL-003)
Error: Nothing matched for clock_name (SEL-005)
Warning: Nothing implicitly matched 'clkr_l' (SEL-003)
Error: Nothing matched for clock_name (SEL-005)
Warning: Nothing implicitly matched 'clkr_h' (SEL-003)
Error: Nothing matched for clock_name (SEL-005)
Warning: Nothing implicitly matched 'clkr_h' (SEL-003)
Error: Nothing matched for clock_name (SEL-005)
Warning: Nothing implicitly matched 'clkr_l' (SEL-003)
Error: Nothing matched for clock_name (SEL-005)
Warning: Nothing implicitly matched 'clkr_l' (SEL-003)
Error: Nothing matched for clock_name (SEL-005)
Warning: Nothing implicitly matched 'clkr_h' (SEL-003)
都是类似于这样的错误
是不是没有把Verilog读进去?
DC定义的时钟是在综合网表上的，ICC之后这些cell或者net被优化掉或者改变了名字，所以报错。你去ICC后的网表里，看看能不能找到 U4IM/u1/add_309/n13即可证实
肯定读了，请问下pt如果出了很多setup时间的error该怎么改呀
懂了。按照你说的找到原因了，谢谢，请问下pt出很多建立时间的错误该怎么改呀?
时钟定义点的处理：一般前端设计人员必须很清楚时钟定义点在哪里，设计的时候应该在RTL里直接调用库的buffer,invertor,MUX等等作为时钟节点，综合时设置dont touch。这样在DC，ICC，PT所有流程中，时钟定义点不会被改变，从而无需反复修改时钟定义点。
setup violation, 改进RTL设计或者加紧约束重新综合或者ICC修，方法都是这么几个。
icc建立时间过了呀，在PT里又差好多
那就是肯定没读对啊，否则不会找不到的，
signoff以pt为准，找到错误原因，返回eco,
请问下pt出error说Error: unknown option '-hsc' (CMD-010)Error: extra positional option 'U1@add_9_root_add_0_root_add_1108/carry[12]' (CMD-012)
Information: script '/home/yzliu/Baseband/icc/exports/tx.sdc'
stopped at line 30494 due to error. (CMD-081)
我看了下sdc文件，就是sdc文件中set_resistance -max 0.00045{get_nets -hsc @ {U1@add_18/carry[11]}
set_load -min 0.00054{get_nets -hsc @ {U1@add_18/carry[11]}
就是这两句读不了，不知道为什么，是因为版本问题吗?
Error: unknown option '-hsc' (CMD-010)
Error: extra positional option 'U1@add_9_root_add_0_root_add_1108/carry[12]' (CMD-012)
Information: script '/home/yzliu/Baseband/icc/exports/tx.sdc'
stopped at line 30494 due to error. (CMD-081)
现在pt就是这两个error。
这两个error对应的sdc文件是set_resistance -max 0.00045 {get_nets -hsc @{U1@add_18/carry[11]}
set_load -min 0.00054 {get_nets -hsc @{U1@add_18/carry[11]}