请教一个DC的问题，DC做STA，某一或非门异常大，请各位大神分析一下

各位大神：本人在使用DC综合一个自己写的电路时，出现了某一或非门延迟异常大，22ns的情况，请教一下各位大神，应该从哪些方面去考虑解决这个问题。
时序路径如下：
****************************************
Report : timing
-path full
-delay max
-max_paths 1
Design : openmips
Version: H-2013.03-SP1
Date: Tue Aug 25 16:01:28 2015
****************************************
# A fanout number of 1000 was used for high fanout net computations.
Operating Conditions: typicalLibrary: smic18_tt
Wire Load Model Mode: segmented
Startpoint: if_id0/id_inst_reg[29]
(rising edge-triggered flip-flop clocked by clk)
Endpoint: id_ex0/ex_aluop_reg[0]
(rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Des/Clust/PortWire Load ModelLibrary
------------------------------------------------
CP0reference_area_20000smic18_tt
LLbitreference_area_20000smic18_tt
hilo_regreference_area_20000smic18_tt
mem_wbreference_area_20000smic18_tt
ex_memreference_area_100000 smic18_tt
divreference_area_100000 smic18_tt
id_exreference_area_20000smic18_tt
regfilereference_area_1000000
smic18_tt
IF_IDreference_area_20000smic18_tt
openmipsreference_area_1000000
smic18_tt
pcreference_area_20000smic18_tt
IDreference_area_100000 smic18_tt
ctrlreference_area_20000smic18_tt
PointIncrPath
-----------------------------------------------------------
clock clk (rise edge)0.000.00
clock network delay (ideal)0.000.00
if_id0/id_inst_reg[29]/CK (FFDHD4X)0.00 #0.00 r
if_id0/id_inst_reg[29]/QN (FFDHD4X)0.150.15 f
if_id0/U5/Z (INVHD8X)0.070.22 r
if_id0/id_inst[29] (IF_ID)0.000.22 r
id0/inst_i[29] (ID)0.000.22 r
id0/U36/Z (AND4HD2X)0.160.39 r
id0/U58/Z (AND2HD4X)0.110.49 r
id0/U718/Z (NAND4B1HD2X)0.150.65 r
id0/U170/Z (OAI21HD4X)0.090.74 f
id0/U490/Z (NOR2HD1X)22.0422.78 r
id0/U489/Z (XNOR2HD1X)7.2930.06 f
id0/U484/Z (AND4HD1X)0.3830.44 f
id0/U482/Z (NAND2HD1X)0.1630.60 r
id0/U214/Z (NAND2HD1X)0.1130.71 f
id0/stall (ID)0.0030.71 f
control/stallreq_from_id (ctrl)0.0030.71 f
control/U4/Z (AOI21B2HD2X)0.3731.08 f
control/stall[2] (ctrl)0.0031.08 f
id_ex0/stall[2] (id_ex)0.0031.08 f
id_ex0/U215/Z (NOR3HD4X)2.9234.00 r
id_ex0/U214/Z (NOR4B1HD4X)2.4436.44 f
id_ex0/U209/Z (AOI22HDLX)0.7637.20 r
id_ex0/U208/Z (INVHDPX)0.0337.23 f
id_ex0/ex_aluop_reg[0]/D (FFDQHD1X)0.0037.23 f
data arrival time37.23
clock clk (rise edge)20.0020.00
clock network delay (ideal)0.0020.00
clock uncertainty-1.0019.00
id_ex0/ex_aluop_reg[0]/CK (FFDQHD1X)0.0019.00 r
library setup time-0.4318.57
data required time18.57
-----------------------------------------------------------
data required time18.57
data arrival time-37.23
-----------------------------------------------------------
slack (VIOLATED)-18.66

1
请各位大神分析一下，这个问题怎么解决

自顶一下 等大神

可能是那个地方的fanout太大了吧。试试约束一下fanout?

fanout，slew太大造成的吧

compile_ultra -incr优化下

换了一个库文件缺好了。从ss换成了tt。具体什么原因还是不太清楚，fanout也不大，可能是compile过程中参数设置有问题吧。谢谢各位。

2013.03 DRV默认流程修不干净，要么升级版本要么再跑一次 -incr -design_rule_only