有坛友熟悉奥地利微电子AMS H18工艺的吗？

没做过，不过0.18 能有多滑头呢，都差不多的

里面有些DRC错误一直解决不了。TG=thick gate layerPC=POLYRX=ODcheck GRTG267_HV
(((NW touching TG) touching (PC over RX)) not over DNmust be tied down by the time M1 is complete.
valid tie down 1 : pdiff in NW is connected to ndiff in substrate by m1
valid tie down 2:ndiff in NW (ntap) is connected to ndiff in substrate by m1( or straddle NW edge)
valid tie down 3 : ndiff/pdiff in NW is connected to ptap in substrate by m1( or pdiff straddles NW edge


这个错误不知怎么下手小编大大了解吗?

这是我在rule文件中找到的关于这一条rule的 定义
// TG267_HV//
//XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
//
x_nw_to_tie_1 = ((NW NOT GRLOGIC) OR (NW INTERACT BB)) INTERACT gate
x_nw_to_tie= NW INTERACT x_nw_to_tie_1
x_optionnal_nw_to_tie = NW INTERACT (((NW NOT GRLOGIC) OR (NW INTERACT BB)) NOT INTERACT gate)
// First possible tie down for GR267
//
// H18REV5
x_ndiff_for_267_td1 = ndiff NOT (NW OR (DN OR (BB OR (BFMOAT OR RXHV))))
//x_ndiff_for_267_td1 = ndiff NOT (NW OR (PI OR (BB OR BFMOAT)))
x_pdiff_in_nwell = (pdiff AND NW) NOT PC
x_ndiff_in_nwell = (ndiff AND NW) NOT PC

CONNECT pcop_res M1 BY ca_all
CONNECT rxop_res M1 BY ca_all

CONNECT M1 x_ndiff_for_267_td1 BY ca_all
CONNECT M1 x_ndiff_in_nwell BY ca_all
CONNECT x_ndiff_in_nwell x_ndiff_for_267_td1
CONNECT M1 x_pdiff_in_nwell BY ca_all

x_valid_267_td1 = NET AREA RATIO x_pdiff_in_nwell x_ndiff_for_267_td1 > 0

// Second possible tie down for GR267

// H18REV5
// DN / RXHV
//x_ndiff_for_267_td2_1 = (ndiff OUTSIDE (NW OR (PI OR (BB OR BFMOAT))))
//OR (((ndiff CUT NW) NOT NW) OUTSIDE (NW OR (PI OR (BB OR BFMOAT))))
//x_ndiff_for_267_td2_2 = (ndiff NOT ((PI OR BB) OR BFMOAT)) CUT NW
x_ndiff_for_267_td2_1 = (ndiff OUTSIDE (NW OR (DN OR (BB OR (BFMOAT OR RXHV)))))
OR (((ndiff CUT NW) NOT NW) OUTSIDE (NW OR (DN OR (BB OR (BFMOAT OR RXHV)))))
//
x_ndiff_for_267_td2_2 = (ndiff NOT ((PI OR BB) OR BFMOAT)) CUT NW
x_ndiff_for_267_td2 = x_ndiff_for_267_td2_1 OR x_ndiff_for_267_td2_2

CONNECT M1 x_ndiff_for_267_td2 BY ca_all
CONNECT RX x_ndiff_for_267_td2
CONNECT x_ndiff_for_267_td2 x_ndiff_in_nwell

x_valid_267_td2 = NET AREA RATIO x_ndiff_in_nwell x_ndiff_for_267_td2 > 0

// Third possible tie down for GR267
// Third possible tie down for GR267

// H18REV5
// DN/RXHV
//x_sxcont_for_267_td3_1 = sxcont NOT (NW OR (PI OR (BB OR BFMOAT)))
//x_sxcont_for_267_td3_2 = (pdiff NOT (PI OR (BB OR BFMOAT))) CUT NW
x_sxcont_for_267_td3_1 = sxcont NOT (NW OR (DN OR (BB OR (BFMOAT OR RXHV))))
x_sxcont_for_267_td3_2 = (pdiff NOT (DN OR (BB OR (BFMOAT OR RXHV)))) CUT NW
//
x_diff_in_nwell = x_pdiff_in_nwell OR x_ndiff_in_nwell
x_sxcont_for_267_td3 = x_sxcont_for_267_td3_1 OR x_sxcont_for_267_td3_2

CONNECT M1 x_sxcont_for_267_td3 BY ca_all
CONNECT RX x_sxcont_for_267_td3
CONNECT M1 x_diff_in_nwell BY ca_all
CONNECT x_sxcont_for_267_td3 x_diff_in_nwell

x_valid_267_td3 = NET AREA RATIO x_diff_in_nwell x_sxcont_for_267_td3 > 0
//
// AMS : not over DN
//
x_nwtg_to_tie = ((NW INTERACT TG) INTERACT gate) NOT DN

CONNECT NW x_valid_267_td1
CONNECT NW x_valid_267_td2
CONNECT NW x_valid_267_td3
CONNECT NW PI

CONNECT x_nwtg_to_tie x_valid_267_td1
CONNECT x_nwtg_to_tie x_valid_267_td2
CONNECT x_nwtg_to_tie x_valid_267_td3
CONNECT x_nwtg_to_tie PI

GRTG267_HV {@ (((NW touching TG) touching (PC over RX)) not over DN
@ must be tied down by the time M1 is complete.
@ valid tie down 1 : pdiff in NW is connected to ndiff in substrate by m1
@ valid tie down 2:ndiff in NW (ntap) is connected to ndiff in substrate by m1( or straddle NW edge)
@ valid tie down 3 : ndiff/pdiff in NW is connected to ptap in substrate by m1( or pdiff straddles NW edge)
NET AREA RATIO x_nwtg_to_tie OVER x_valid_267_td1 x_valid_267_td2 x_valid_267_td3 == 0 }

小编在吗

不是特别清楚，发layout版面看看吧