为什么ENCOUNTER不能修正以下的HOLD TIME？

这是一个CLOCK GATING HOLD 违例，时间也不是很大，0.4ns左右。
按理说工具可以简单的加一个DELAY CELL或者若干INV就可以解决了，但为啥它就不修呢?
我已经反复地执行optDesign -hold了，没用。

1. Path 1: VIOLATED Clock Gating Hold Check with Pin u217/B
   
2. Endpoint:u217/AN(v) checked with trailing edge of 'SYS_CLK'
   
3. Beginpoint: cpu_clk_gate_reg/Q (v) triggered by trailing edge of 'SYS_CLK'
   
4. Path Groups:{clkgate}
   
5. Other End Arrival Time20.039
   
6. + Clock Gating Hold0.200
   
7. + Phase Shift0.000
   
8. + Uncertainty0.300
   
9. = Required Time20.539
   
10. Arrival Time20.141
    
11. Slack Time-0.398
    
12. Clock Fall Edge20.000
    
13. = Beginpoint Arrival Time20.000
    
14. Timing Path:
    
15. +----------------------------------------------------------------------------------+
    
16. |Instance|Arc|Cell|Slew | Delay | Arrival | Required |
    
17. ||||||Time|Time|
    
18. |------------------+-------------+------------+-------+-------+---------+----------|
    
19. | clksw3_m| clk_out v| clksw3|||20.000 |20.398 |
    
20. | cpu_clk_gate_reg | GN v -> Q v | LATNHD1X| 0.046 | 0.141 |20.141 |20.539 |
    
21. | u217| AN v| NOR2B1HD1X | 0.046 | 0.000 |20.141 |20.539 |
    
22. +----------------------------------------------------------------------------------+
    
23. Clock Fall Edge20.000
    
24. = Beginpoint Arrival Time20.000
    
25. Other End Path:
    
26. +-------------------------------------------------------------------------+
    
27. | Instance |Arc|Cell|Slew | Delay | Arrival | Required |
    
28. ||||||Time|Time|
    
29. |----------+------------+------------+-------+-------+---------+----------|
    
30. | clksw3_m | clk_out v| clksw3|||20.000 |19.602 |
    
31. | u216| A v -> Z ^ | INVHDPX| 0.061 | 0.039 |20.039 |19.641 |
    
32. | u217| B ^| NOR2B1HD1X | 0.061 | 0.000 |20.039 |19.641 |
    
33. +-------------------------------------------------------------------------+

复制代码

自己手动加一个呢?

可能他有setup violation的风险 ，搞不定就手工加吧

good job