siliconsmart工具import failed请教
Error:parse failed : 5
Warning: The port A is not in the node map. It may be a floating port.
Warning: The port Q is not in the node map. It may be a floating port.
Warning: The port A is not in the node map. It may be a floating port.
Warning: The port Q is not in the node map. It may be a floating port.
Info:Parsing SPICE netlist(s) for cell 'INJIX0': /mnt/datacenter/design33/project/product/nvram/csm32k5v/csm32k5v_a1x/dig/wxiao/nvram/lib/my_try/runtime/fr/netlists/INJIX0.cdl
Warning: The port type(direction) of "a" defined in .subckt line of the netlist for cell:INJIX0 could not be ascertained.
Warning: The port type(direction) of "q" defined in .subckt line of the netlist for cell:INJIX0 could not be ascertained.
Warning: Ignoring cell INJIX0...
Info:**** FR Summary ****
Info:Import completed. 0 of 1 cells recognized fully. 1 cell(s) may be incomplete. 0 cell(s) failed. 0 cell(s) could not be updated.
Info:The following cell(s) are incomplete
Info:INJIX0
Warning: Warning: Couldn't run egrep on /mnt/datacenter/design33/project/product/nvram/csm32k5v/csm32k5v_a1x/dig/wxiao/nvram/lib/my_try/runtime/fr/fr.localhost.4098/talus.1.log]
Info:Please see /mnt/datacenter/design33/project/product/nvram/csm32k5v/csm32k5v_a1x/dig/wxiao/nvram/lib/my_try/runtime/fr/fr.localhost.4098.log for more info...
Info:Completed 1 tasks (0 successful, 1 failed, 0 killed) covering 1 cell(s).
Info:Results summary:
Info:Cell INJIX0: 1 total tasks, 0 completed (0 cache hits), 0 killed, 1 failed, 0 remaining.
Cdl网表
************************************************************************
* auCdl Netlist:
*
* Library Name:D_CELLS_JI
* Top Cell Name: INJIX0
* View Name:cmos_sch
* Netlisted on:Apr 11 17:02:05 2012
************************************************************************
*.BIPOLAR
*.RESI = 1
*.RESSIZE
*.CAPVAL
*.DIOPERI
*.DIOAREA
*.EQUATION
*.LDD
*.SCALE METER
.PARAM
*.GLOBAL VDD
+VSS
*.PIN VDD
*+VSS
************************************************************************
* Library Name: GATES_HV
* Cell Name:invrk
* View Name:schematic
************************************************************************
.SUBCKT invrk in out VSSO VDDO
*.PININFO in:I out:O VSSO:B VDDO:B
MMN1 out in VSSO VSSO NEI W=GT_PDW L=GT_PDL M=1.0
+ AD=sx*(GT_PDW) AS=sx*(GT_PDW) PD=2*(sx+(GT_PDW)) PS=2*(sx+(GT_PDW))
+ NRD=lc/(GT_PDW) NRS=lc/(GT_PDW)
MMP1 out in VDDO VDDO PEI W=GT_PUW L=GT_PUL M=1.0
+ AD=sx*(GT_PUW) AS=sx*(GT_PUW) PD=2*(sx+(GT_PUW)) PS=2*(sx+(GT_PUW))
+ NRD=lc/(GT_PUW) NRS=lc/(GT_PUW)
.ENDS
************************************************************************
* Library Name: D_CELLS_JI
* Cell Name:INJIX0
* View Name:cmos_sch
************************************************************************
.SUBCKT INJIX0 A Q
*.PININFO A:I Q:O
Xin_1 A Q VSS VDD / invrk GT_PUL=180.00n GT_PUW=810.00n lc=2.7e-07
+ sx=4.8e-07 GT_PDL=180.00n GT_PDW=290.0n
.ENDS
SPICE MODEL
* ----------------------------------------------------------------------
************* XFAB ******** MODEL PARAMETERS ***************************
* ----------------------------------------------------------------------
* Simulator : HSPICE version: C-2009.3 32-BIT
* Device: ne3i
* Model: BSIM3V3 version 3.24 Binned
* Process: XH018
* Extracted : Wafer: X-FAB Sarawak Sdn. Bhd.
* Spec.: PS_018_03
* Revision: 2.0.3; 2009-11-30; ED5B20B4
* ----------------------------------------------------------------------
*PARAMETERIZED
* ----------------------------------------------------------------------
* Flicker noise parameters are included,
* default noimod=2 BSIM3v3, when noimod=1 SPICE2
* TNOM = 27 deg C
*
.subckt nei d g s b w=1e-6 l=1e-6 ad=-1 as=-1 pd=-1 ps=-1 nrd=-1 nrs=-1
+ par1=1 wcd_avt=0 wcd_au0=0
.param adl='(ad>=0)?ad0.48e-6*w)'
+asl='(as>=0)?as0.48e-6*w)'
+pdl='(pd>=0)?pd(2*w)+0.96e-6)'
+psl='(ps>=0)?ps:((2*w)+0.96e-6)'
+nrdl='(nrd>=0)?nrd:(0.27e-6/w)'
+nrsl='(nrs>=0)?nrs:(0.27e-6/w)'
m1 d g s b neimos w=w l=l ad=adl as=asl pd=pdl ps=psl nrd=nrdl nrs=nrsl
+ delvto='(Avt_ne3i+wcd_avt)/sqrt(par1*1e12*(w+0.000e+00)*(l+0.000e+00))'
+ mulu0='1+(Au0_ne3i+wcd_au0)/sqrt(par1*1e12*(w+0.000e+00)*(l+0.000e+00))'
.model neimos.1 nmos
+ version=3.24level=49
+ lmin=3.5E-7lmax=2.0001E-4
+ wmin=2.2E-7wmax=2.0001E-4
+ mobmod=1capmod=3
+ nqsmod=0binunit=2
+ tnom=27
+ xl='xl_nei'xw='xw_nei'
+ lmlt=1wmlt=1
+ tox='tox_nei'toxm='tox_nei'
+ wint=2.643874E-8lint=1.04E-8
+ wl=0wln=1ww=0
+ wwn=1wwl=0ll=0
+ lln=1lw=0lwn=1
+ lwl=0llc=0lwc=0
+ lwlc=0wlc=0wwc=0
+ wwlc=0hdif=2.7E-7ldif=1E-7
+ vth0='vth0_d_nei+(0.734242)'lvth0=-4.043204E-8
+ wvth0=-2.189923E-8pvth0=1.652422E-15
+ k1=0.894145lk1=8.894162E-8
+ wk1=-1.251247E-8pk1=-1.455803E-14
+ k2=3.41776E-2lk2=-9.702383E-8
+ wk2=-1.481687E-9pk2=7.719637E-15
+ k3=-1.03023E-2lk3=3.391508E-9
+ wk3=1.02478E-7pk3=-3.373575E-14
+ k3b=-2.12054E-2lk3b=6.980806E-9
+ wk3b=2.109324E-7pk3b=-6.943894E-14
+ nlx=1.33439E-7
+ dvt0=8.2
+ dvt1=0.52826
+ dvt2=0
+ dvt0w=0
+ dvt1w=5.8058E-18
+ dvt2w=0
+ u0='u0_m_nei*(3.44495E-2)'lu0='u0_m_nei*(2.7815E-9)'
+ wu0='u0_m_nei*(-9.11044E-11)'pu0='u0_m_nei*(1.330653E-15)'
+ ua=-8.743551E-10lua=-5.004806E-17
+ wua=6.651215E-17pua=-2.063677E-23
+ ub=2.283881E-18lub=2.141291E-25
+ wub=-6.322433E-26pub=-9.227258E-32
+ uc=1.353986E-10luc=-6.070135E-18
+ wuc=-1.072884E-17puc=-4.849621E-24
+ voff='voff_m_nei*(-9.59072E-2)'lvoff='voff_m_nei*(-1.005488E-8)'
+ wvoff='voff_m_nei*(-8.162537E-9)'pvoff='voff_m_nei*(3.015038E-15)'
+ nch=6.657216E17
+ nfactor=0.2061lnfactor=6.924953E-13
+ wnfactor=3.51554E-13pnfactor=-1.157316E-19
+ cit=2.332338E-3
+ cdsc=0
+ cdscb=0
+ cdscd=0
+ xj=1.5E-7w0=0
+ prwg=0
+ prwb=0
+ wr=1
+ rdsw=488.1414
+ a0=1.092551la0=-2.739012E-7
+ wa0=1.548346E-8pa0=4.02216E-15
+ ags=0.229299lags=-4.368452E-8
+ wags=-2.094278E-9pags=1.64652E-14
+ a1=0
+ a2=1
+ b0=0
+ b1=0
+ vsat=1.028092E5lvsat=-8.898565E-4
+ wvsat=-1.49025E-5pvsat=1.48715E-10
+ keta=1.387295E-3lketa=1.796008E-9
+ wketa=-4.854769E-9pketa=-5.92392E-16
+ dwg=0
+ dwb=0
+ alpha0=3.6816E-6
+ beta0=24.83
+ pclm=1.41126lpclm=-2.043799E-8
+ wpclm=-2.037229E-8ppclm=2.032992E-13
+ pdiblc1=0.1
+ pdiblc2=3.971746E-4
+ pdiblcb=0
+ drout=1
+ pvag=0
+ pscbe1=5.68715E8lpscbe1=-96.778646
+ wpscbe1=-1.62076ppscbe1=1.617389E-5
+ pscbe2=-1.835607E-8lpscbe2=2.829709E-13
+ wpscbe2=4.738938E-15ppscbe2=-4.729081E-20
+ delta=5E-4
+ eta0=0
+ etab=-1.31681E-2letab=-1.359502E-9
+ wetab=5.310028E-11petab=-3.030303E-16
+ dsub=0.198846ldsub=3.442928E-14
+ wdsub=-6.370682E-15pdsub=2.331991E-19
+ alpha1=9.68
+ ckappa=0.6
+ cf=0
+ clc=1E-7
+ cle=0.6
+ dlc=0
+ dwc=0
+ vfbcv=-1.000589
+ noff=1
+ voffcv=0
+ acde=1
+ moin=15
+ elm=5
+ kt1=-0.344086lkt1=8.044705E-9
+ wkt1=-4.68622E-11pkt1=1.352834E-15
+ kt1l=0
+ kt2=-6.10561E-2lkt2=1.119756E-8
+ wkt2=-1.241139E-10pkt2=-1.04186E-16
+ ute=-1.383802lute=8.996781E-9
+ wute=-7.052956E-10pute=-1.639887E-15
+ ua1=2.808777E-9lua1=2.312708E-17
+ wua1=2.767903E-18pua1=-3.944213E-24
+ ub1=-3.231617E-18lub1=-1.498428E-25
+ wub1=-5.339412E-26pub1=2.514158E-32
+ uc1=-1.02349E-10luc1=1.05519E-17
+ wuc1=9.607874E-19puc1=-1.763461E-24
+ at=4.115326E4lat=-9.779028E-3
+ wat=1.614063E-4pat=1.142498E-9
+ prt=0
+ noimod=2
+ ef=1.01
+ noia=3.3E20noib=6.9809E4noic=-5.2E-13
+ acm=13nj=1.5xpart=1
+ rsh=5.8js=1.41E-5jsw=1.29E-11
+ cgdo='cgdo_ne3i'
+ cgdl='0.000e+00'
+ cgso='cgso_ne3i'
+ cgsl='0.000e+00'
+ cgbo=0
+ cj='cj_nei'cjsw='cjsw_nei'cjswg='cjswg_nei'
+ tcj=7.413e-04tcjsw=8.086e-04tcjswg=5.233e-04
+ mj=3.500e-01mjsw=2.400e-01mjswg=2.580e-01
+ pb=9.000e-01pbsw=6.900e-01pbswg=4.241e-01
+ tpb=1.726e-03tpbsw=2.366e-03tpbswg=1.391e-03
+ xti=3.000e+00tlev=1.000e+00tlevc=1.000e+00
*
.ends nei
* ----------------------------------------------------------------------
难道用siliconsmart的工具的人不多吗?都是用ncx工具的?
无法导入（import）cdl文件，是什么原因?
直接导入你那个cdl网表好像不行，你可以将
.SUBCKT invrk in out VSSO VDDO
*.PININFO in:I out:O VSSO:B VDDO:B
MMN1 out in VSSO VSSO NEI W=GT_PDW L=GT_PDL M=1.0
+ AD=sx*(GT_PDW) AS=sx*(GT_PDW) PD=2*(sx+(GT_PDW)) PS=2*(sx+(GT_PDW))
+ NRD=lc/(GT_PDW) NRS=lc/(GT_PDW)
MMP1 out in VDDO VDDO PEI W=GT_PUW L=GT_PUL M=1.0
+ AD=sx*(GT_PUW) AS=sx*(GT_PUW) PD=2*(sx+(GT_PUW)) PS=2*(sx+(GT_PUW))
+ NRD=lc/(GT_PUW) NRS=lc/(GT_PUW)
.ENDS
单独保存为 INJIX0.cir
然后 import -netlist INJIX0.cir 一般就能导入成功了
或者直接 copy INJIX0.cir到。/netlists/ 下即可 （前提是你先有INJIX0.inst
）
然后在configure.tcl 中修改仿真器和model路径
我也在自己摸索，希望能提供点帮助
谢谢，先试试看，还有就是我在用icfb export cdl网表时，如果选择digital就总是failed，如果选择默认的analog，就能successful，是不是这和pdk有关系啊?
我一般是建立一个schemtic ,调入需要提参的单元，然后用 analog design environment 选择 hspiceD 仿真器 create netlist 得到 .subckt的 hspice网表 可以参考 《数字VLSI芯片设计—使用Cadence和Synopsys CAD工具_[E.Brunvand 著][电子工业出版社][2009][383页].pdf》 一书 的 单元表证 章节。
另外，求教一下是否采用 spectre 作为仿真器 提取过单元参数?
最近一直没有试成功 ，hspice的试成功过。
我用的cadence中的ADE的spectre仿真器仿真时，仿真器会在当前目录下提取生成.scs文件，该文件中就包括spectre网表
回复 7# sdwsh1
siliconsmart 几种常用的仿真器都支持的，应该是你哪里设置不对。
请问一下小编，SiliconSmart 能够做模拟模块的特征化吗?
非常感谢您的解答！
不能
哦，明白了，谢谢！
那请问模拟电路的特征化用什么工具可以做呢?
very good
明白了，谢谢