哪位大侠帮我看看pt的timing report。这个该怎么修
时间:10-02
整理:3721RD
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------------- Max Corner PrimeTime ----------------
****************************************
Report : timing
-path_type full
-delay_type max
-max_paths 1
Design : m_core
Version: H-2012.12
Date: Sat Jul 12 19:46:34 2014
****************************************
Startpoint: por (input port clocked by insclk)
Endpoint: u_spi_out/u_irq_gen/u_navscc_cnt/div_x_cnt_reg_1_
(recovery check against rising-edge clock iclk)
Path Group: **async_default**
Path Type: max
PointIncrPath
------------------------------------------------------------------------------
clock insclk (rise edge)0.00.0
clock network delay (ideal)0.00.0
input external delay10.010.0 f
por (in)0.0 &10.0 f
U110/Z (BUFM2)1.2 &11.2 f
U102/Z (BUFM2)1.3 &12.6 f
U105/Z (INVM2)1.5 &14.0 r
u_spi_out/IN8 (m_spi_out)0.0 &14.0 r
u_spi_out/u_irq_gen/por (f_irq_gen)0.0 &14.0 r
u_spi_out/u_irq_gen/u_navscc_cnt/por (f_navscc_cnt)0.0 &14.0 r
u_spi_out/u_irq_gen/u_navscc_cnt/U37/Z (AN3M2)1.9 &15.9 r
u_spi_out/u_irq_gen/u_navscc_cnt/U120/Z (BUFM2)1.8 &17.8 r
u_spi_out/u_irq_gen/u_navscc_cnt/div_x_cnt_reg_1_/RB (DFQRM1)
0.0 &17.8 r
data arrival time17.8
clock iclk (rise edge)1.01.0
clock network delay (ideal)0.01.0
u_spi_out/u_irq_gen/u_navscc_cnt/div_x_cnt_reg_1_/CK (DFQRM1)1.0 r
library recovery time-0.20.8
data required time0.8
------------------------------------------------------------------------------
data required time0.8
data arrival time-17.8
------------------------------------------------------------------------------
slack (VIOLATED)-16.9
****************************************
Report : timing
-path_type full
-delay_type max
-max_paths 1
Design : m_core
Version: H-2012.12
Date: Sat Jul 12 19:46:34 2014
****************************************
Startpoint: por (input port clocked by insclk)
Endpoint: u_spi_out/u_irq_gen/u_navscc_cnt/div_x_cnt_reg_1_
(recovery check against rising-edge clock iclk)
Path Group: **async_default**
Path Type: max
PointIncrPath
------------------------------------------------------------------------------
clock insclk (rise edge)0.00.0
clock network delay (ideal)0.00.0
input external delay10.010.0 f
por (in)0.0 &10.0 f
U110/Z (BUFM2)1.2 &11.2 f
U102/Z (BUFM2)1.3 &12.6 f
U105/Z (INVM2)1.5 &14.0 r
u_spi_out/IN8 (m_spi_out)0.0 &14.0 r
u_spi_out/u_irq_gen/por (f_irq_gen)0.0 &14.0 r
u_spi_out/u_irq_gen/u_navscc_cnt/por (f_navscc_cnt)0.0 &14.0 r
u_spi_out/u_irq_gen/u_navscc_cnt/U37/Z (AN3M2)1.9 &15.9 r
u_spi_out/u_irq_gen/u_navscc_cnt/U120/Z (BUFM2)1.8 &17.8 r
u_spi_out/u_irq_gen/u_navscc_cnt/div_x_cnt_reg_1_/RB (DFQRM1)
0.0 &17.8 r
data arrival time17.8
clock iclk (rise edge)1.01.0
clock network delay (ideal)0.01.0
u_spi_out/u_irq_gen/u_navscc_cnt/div_x_cnt_reg_1_/CK (DFQRM1)1.0 r
library recovery time-0.20.8
data required time0.8
------------------------------------------------------------------------------
data required time0.8
data arrival time-17.8
------------------------------------------------------------------------------
slack (VIOLATED)-16.9
这个是个异步的clk之间的检查,首先你得确认这条路径是不是false path. 其次你的clock还是ideal的,你这个data是pr之前的?
是pr之后的,没设false path.我需要改sdc吗?
和前端的人讨论
直接false path,
然后问前端
clock都还是ideal的你看这个报告有啥意义?
sdc还是不能直接用DC的
