在PT中report_timing报sequential_clock_pulse_width，怎么修啊

Is the clock 50-50 duty cycle?
I thought that is gated clock. If the gated clock you may be fix the rtl code

37-63,没有经过clock_gate

时钟脉宽不够，试试换个DFF，不同类型的DFF对时钟脉宽的要求会不一样。但是好像差异也不大。想不通的是，为啥这个问题会到PT时才发现呢?按理说在DC时就会表现出来了。

What is the running frequency of you clock?
May be your clock to fast the standard cell has the limitation of minimum pulse width.

使用对抗占空比偏差的时钟树结构，准确设置OCV