How to make SoC Encounter export Verilog with VDD/VSS pins
it can be done with "saveNetlist -phys" command instead of GUI.
MAP文件的问题。MAP中没有包括Encounter中所有的层次
really? i can't find the location of StreamOutput.map so that i can't check the content. would you please tell me where can i find it? thx
1. foundry提供,
2. 如果没提供,就自己改一个,
先默认生成一个streamout, 然后对照着virtuoso里面的layer层改。
is it caused by uncorrect map file ? but the module present VDD/VSS pin when i export with the "svaNestlist -phys" command, as following:
assign OpMode[1] = 1'b0 ;
assign OpMode[0] = 1'b0 ;
// Module instantiations
AOI21X4 U4 (
.Y(n7),
.B0(tx_valid_last),
.A1(n30),
.A0(tx_valid_sr),
.VDD(VDD),
.VSS(VSS));
AND2X2 U20 (
.Y(n9),
.B(n6),
.A(drive_k),
.VDD(VDD),
.VSS(VSS));
usbf_utmi_ls u0 (
.clk(phy_clk),
.rst(rst),
.resume_req(resume_req),
.rx_active(rx_active),
.tx_ready(tx_ready),
.drive_k(drive_k),
.XcvSelect(XcvSelect),
.TermSel(TermSel),
.SuspendM(SuspendM),
.LineState({ LineState[1],
LineState[0] }),
.OpMode(),
.usb_vbus(usb_vbus),
.mode_hs(mode_hs),
.usb_reset(usb_reset),
.usb_suspend(usb_suspend),
.usb_attached(usb_attached),
.VDD(VDD),
.VSS(VSS));
svaNestlist -phys 就够了,小编是教学帖把?
我不知道你是不是在讽刺我,还是真的saveNetlist -phys就够了,反正我用saveNetlist -phys是可以的。
不是教学贴,是自己写方便以后查,写下来自己印象深,
看了你的回复才发现,和我想说的语气不一样~
我是想说你那条语句就可以解决那种情况了二楼不知所云map文件是控制gds的吧?
喔,谢谢哈