求助：primetime的问题

我将top.v global.v local.v三个netlist文件读到pt中，top.v中有global和local的实例化模块。读进去之后link，然后我想对global和local分别读入ICC产生的.SPEF寄生文件。我就current_design global，这时候他就报错说找不到global。Local也是一样的错误。local和global的版图我是分别产生的，所以spef有两个，而且是针对子模块的线名定义的，所以下面会出现一大堆的读入read_parasitics的错误。我运行list_design,显示出来的只有top这个design。求助啊，很急，先谢谢大大们了。下面是我的部分script：
... ...
read_verilog $local_netlist_path/local_post_layout.v
read_verilog $global_netlist_path/global_post_layout.v
read_verilog /home/zenglei/projects_dig/telestim108a/pt_post_layout/telestim108a_top.v
link
source $script_path/constraint.tcl
current_design local_controller
read_parasitics $local_netlist_path/local_finish.spef.max
current_design global_controller
read_parasitics $global_netlist_path/global_finish.spef.max
current_design telestim108a_top
... ...
##################################################
run.log文件
read_verilog $local_netlist_path/local_post_layout.v
Loading verilog file '/home/zenglei/projects_dig/telestim108a/local_layout/report/local_post_layout.v'
1
read_verilog $global_netlist_path/global_post_layout.v
Loading verilog file '/home/zenglei/projects_dig/telestim108a/global_layout/report/global_post_layout.v'
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read_verilog /home/zenglei/projects_dig/telestim108a/pt_post_layout/telestim108a_top.v
Loading verilog file '/home/zenglei/projects_dig/telestim108a/pt_post_layout/telestim108a_top.v'
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link
Loading db file '/home/zenglei/projects_dig/telestim108a/lib/synopsys/D_CELLS_MOS_slow_3_00V_125C.db'
Loading db file '/tools/synopsys/syn08094/libraries/syn/standard.sldb'
Loading db file '/home/zenglei/projects_dig/telestim108a/lib/synopsys/D_CELLS.sdb'
Linking design telestim108a_top...
Information: Removing 4 unneeded designs..... (LNK-034)
Information: 660 (90.78%) library cells are unused in library D_CELLS_MOS_slow_3_00V_125C.....
Information: total 660 library cells are unused.
Information: Issuing set_operating_conditions for setting analysis mode on_chip_variation. (PTE-037)
set_operating_conditions -analysis_type on_chip_variation-library [get_libs {D_CELLS_MOS_slow_3_00V_125C.db_CELLS_MOS_slow_3_00V_125C}]
Removed 3909 unconnected cells and blackboxes.
Design 'telestim108a_top' was successfully linked.
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source $script_path/constraint.tcl
1
current_design local_controller
Error: Cannot find design 'local_controller'. (DES-004)
read_parasitics $local_netlist_path/local_finish.spef.max
Information: Derived library resistance unit is 1.000000 Kohm (Time unit is 1 ns, and Capacitance unit is 1.000000 pF). (DES-028)
Error: Cannot find port/pin 'U6/A' in design 'telestim108a_top' (DES-002)
Error: Cannot find port/pin 'U341/B' in design 'telestim108a_top' (DES-002)
Error: Cannot find port/pin 'add_218/U2/B' in design 'telestim108a_top' (DES-002)
... ...
pt_shell> list_designs

Design Registry:
*L telestim108a_top/home/zenglei/projects_dig/telestim108a/pt_post_layout/telestim108a_top.v:telestim108a_top
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求助啊，大神们！

求解答。很急