ICC在place之后slack为-3.79
**********************************
Sub-Region Utilization
**********************************
Number of regions with placement utilization 0 - 0.125 is 9973 (20.18%)
Number of regions with placement utilization 0.125 - 0.25 is 3091 (6.26%)
Number of regions with placement utilization 0.25 - 0.375 is 4167 (8.43%)
Number of regions with placement utilization 0.375 - 0.5 is 4618 (9.35%)
Number of regions with placement utilization 0.5 - 0.625 is 4283 (8.67%)
Number of regions with placement utilization 0.625 - 0.75 is 3788 (7.67%)
Number of regions with placement utilization 0.75 - 0.875 is 4781 (9.68%)
Number of regions with placement utilization 0.875 - 1 is 14714 (29.78%)
界面看过，有些地方一个cell都没放，有些地方就很挤。
用的命令是
place_opt -power -area_recovery -congestion -effort high
legalize_placement -timing
check_legality -verbose
psynopt -congestion -area_recovery
不知道是什么原因。是我的约束问题还是布局需要调整呢?
请大侠们指教！谢谢！
利用率有点高，布局再调整一下
啊 请教 第一回跑PR的流程 完全没经验 这个利用率已经算高的了么?一般利用率是多少范围以内丫
设一下set_congestion_options -max_util
请问一般有什么经验值推荐吗?设置最大多少
-max_util 0.85
多谢！
Place之后，能控制在75一下， Route之后控制在80%，风险会小一些。
嗯啊 谢谢！
加了这条命令以后重新跑。结果slack涨到-6.02了。
同求答案
看下timing Path,没准是你的Floorpan不合理。
我也怀疑是这个的问题 看了path 2]0H~)8YS.jpg)
稍稍密的地方如下
这个就是之前-3.79的那个path
贴贴timing report，然后分析下！
macro间距太搞了吧，要么有端口，然后加大间距，要么干脆不要放stdcell在里面。
Startpoint:
7501/b2v_inst1/pdam_acq/U1_pdam_acq_acci/U_wrapper_dpram_81x1600/inst_bist/st_reg_0_
(rising edge-triggered flip-flop clocked by clk_124M)
Endpoint:
7501/b2v_inst1/pdam_acq/U1_pdam_acq_acci/U_wrapper_dpram_81x1600/inst_bist/din_reg_118_
(rising edge-triggered flip-flop clocked by clk_124M)
Path Group: clk_124M
Path Type: max
PointIncrPath
--------------------------------------------------------------------------
clock clk_124M (rise edge)0.000.00
clock network delay (ideal)1.501.50
7501/b2v_inst1/pdam_acq/U1_pdam_acq_acci/U_wrapper_dpram_81x1600/inst_bist/st_reg_0_/CK
(FFDQRHDLX)
0.00 #1.50 r
7501/b2v_inst1/pdam_acq/U1_pdam_acq_acci/U_wrapper_dpram_81x1600/inst_bist/st_reg_0_/Q
(FFDQRHDLX)
0.542.04 r
7501/b2v_inst1/pdam_acq/U1_pdam_acq_acci/U_wrapper_dpram_81x1600/inst_bist/U1/Z (BUFHD2X)
0.38 *2.42 r
7501/b2v_inst1/pdam_acq/U1_pdam_acq_acci/U_wrapper_dpram_81x1600/inst_bist/U2/Z (INVHD1X)
0.41 *2.83 f
7501/b2v_inst1/pdam_acq/U1_pdam_acq_acci/U_wrapper_dpram_81x1600/inst_bist/U148/Z
(NAND2HDUX)
0.53 *3.36 r
7501/b2v_inst1/pdam_acq/U1_pdam_acq_acci/U_wrapper_dpram_81x1600/inst_bist/U129/Z
(NOR2HD1X)
0.26 *3.62 f
7501/b2v_inst1/pdam_acq/U1_pdam_acq_acci/U_wrapper_dpram_81x1600/inst_bist/U130/Z
(NOR2B1HDMX)
0.29 *3.91 r
7501/b2v_inst1/pdam_acq/U1_pdam_acq_acci/U_wrapper_dpram_81x1600/inst_bist/U281/Z
(NAND2HDUX)
0.37 *4.28 f
7501/b2v_inst1/pdam_acq/U1_pdam_acq_acci/U_wrapper_dpram_81x1600/inst_bist/U125/Z
(INVCLKHDLX)
0.37 *4.28 f
7501/b2v_inst1/pdam_acq/U1_pdam_acq_acci/U_wrapper_dpram_81x1600/inst_bist/U125/Z
(INVCLKHDLX)
0.32 *4.60 r
7501/b2v_inst1/pdam_acq/U1_pdam_acq_acci/U_wrapper_dpram_81x1600/inst_bist/U579/Z
(OAI211HD1X)
0.21 *4.81 f
7501/b2v_inst1/pdam_acq/U1_pdam_acq_acci/U_wrapper_dpram_81x1600/inst_bist/U56/Z (BUFHD5X)
0.22 *5.03 f
7501/b2v_inst1/pdam_acq/U1_pdam_acq_acci/U_wrapper_dpram_81x1600/inst_bist/U267/Z
(AOI21HDUX)
0.34 *5.37 r
7501/b2v_inst1/pdam_acq/U1_pdam_acq_acci/U_wrapper_dpram_81x1600/inst_bist/U266/Z
(OAI211HDLX)
0.28 *5.65 f
7501/b2v_inst1/pdam_acq/U1_pdam_acq_acci/U_wrapper_dpram_81x1600/inst_bist/U721/Z (BUFHD1X)
0.32 *5.96 f
7501/b2v_inst1/pdam_acq/U1_pdam_acq_acci/U_wrapper_dpram_81x1600/inst_bist/U112/Z (BUFHD8X)
0.34 *6.30 f
7501/b2v_inst1/pdam_acq/U1_pdam_acq_acci/U_wrapper_dpram_81x1600/inst_bist/U556/Z
(BUFHD20X)
0.30 *6.61 f
7501/b2v_inst1/pdam_acq/U1_pdam_acq_acci/U_wrapper_dpram_81x1600/inst_bist/U558/Z (INVHDUX)
3.84 *10.44 r
7501/b2v_inst1/pdam_acq/U1_pdam_acq_acci/U_wrapper_dpram_81x1600/inst_bist/U163/Z (BUFHD3X)
0.93 *11.37 r
7501/b2v_inst1/pdam_acq/U1_pdam_acq_acci/U_wrapper_dpram_81x1600/inst_bist/U214/Z (OR2HD2X)
0.49 *11.86 r
7501/b2v_inst1/pdam_acq/U1_pdam_acq_acci/U_wrapper_dpram_81x1600/inst_bist/din_reg_118_/D
(FFDQRHD2X)
0.01 *11.87 r
data arrival time11.87
clock clk_124M (rise edge)7.007.00
clock network delay (ideal)1.508.50
clock reconvergence pessimism0.008.50
clock uncertainty-0.308.20
7501/b2v_inst1/pdam_acq/U1_pdam_acq_acci/U_wrapper_dpram_81x1600/inst_bist/din_reg_118_/CK
(FFDQRHD2X)
0.008.20 r
library setup time-0.128.08
data required time8.08
--------------------------------------------------------------------------
data required time8.08
data arrival time-11.87
--------------------------------------------------------------------------
slack (VIOLATED)-3.79
我是怕后面会不会需要插buf...所以中间的距离留两排std cell的高度行么?
如果不留会不会后面就近插不了buf有问题
应该是cell太密集了
请问用什么命令能调呢。我也觉得太密 有些地方又很空
你得看macro的pin的朝向再决定
看走线是么 需要不需要留空间?
看macro的pin的位置，，，做fp的时候就要考虑它的朝向如果你面积充足，不建议你图片那样做
图片?
13#中间的照片
是要看macro的pin之间的连接关系留走线么 或者一点间距不留?
两种情况，推荐第一种，是这个意思。明白了么?
那优化万一需要插个buffer肿么办?
优化也是优先端口的，你可以按我说的先试试看，然后再问问题。
还有一个你一上来place就是power_recover area_recover ，这样不太好，应该先优化timing ，再优化power和面积
您的意思是：
place_opt
legalize_placement -timing
check_legality -verbose
psynopt -congestion -area_recovery
place_opt -power -area_recovery -congestion -effort high
这样?不太明白