微波EDA网,见证研发工程师的成长!
首页 > 研发问答 > 微电子和IC设计 > IC后端设计交流 > Astro问题求教,不胜感激!

Astro问题求教,不胜感激!

时间:10-02 整理:3721RD 点击:

小弟后端新手,求高手指教!最近在用Astro做数模混合版图后端的时候(Charterted 0.18的库,模拟的我做成了macro),遇到一个问题,就是总是报有开路节点,LVS报告如下。请问这种错误一般是什么造成的?
-- LVS START : --
Total area error in layer 0 is 0.Elapsed =0:00:00, CPU =0:00:00
Total area error in layer 1 is 0.Elapsed =0:00:00, CPU =0:00:00
Total area error in layer 2 is 0.Elapsed =0:00:00, CPU =0:00:00
Total area error in layer 3 is 0.Elapsed =0:00:00, CPU =0:00:00
Total area error in layer 4 is 0.Elapsed =0:00:00, CPU =0:00:00
Total area error in layer 5 is 0.Elapsed =0:00:00, CPU =0:00:00
Total area error in layer 6 is 0.Elapsed =0:00:00, CPU =0:00:00
Total area error in layer 7 is 0.Elapsed =0:00:00, CPU =0:00:00
Total area error in layer 8 is 0.Elapsed =0:00:00, CPU =0:00:00
Total area error in layer 9 is 0.Elapsed =0:00:00, CPU =0:00:00
Total area error in layer 10 is 0.Elapsed =0:00:00, CPU =0:00:00
Total area error in layer 11 is 0.Elapsed =0:00:00, CPU =0:00:00
Total area error in layer 12 is 0.Elapsed =0:00:00, CPU =0:00:00
ERROR : PortInst u_DVSS VSS(36865) in net VSS(1025) is floating.
** Total Floating ports are 1.
** Total Floating Nets are 0.
** Total SHORT Nets are 0.
ERROR : Logical Net VSS is open.
** This OPEN is caused by PIN. Please check with FLOATING PIN error option.
ERROR : Logical Net VDD is open.
** Total OPEN Nets are 2.
** Total Electrical Equivalent Error are 0.
** Total Must Joint Error are 0.
-- LVS END : --

aprPGConnect不完整,
也可能是false error, 做calibre吧

Copyright © 2017-2020 微波EDA网 版权所有

网站地图

Top