astro新人问题多多
时间：10-02
整理：3721RD
点击：
1.ring 和stripe 的层次有什么说法。我看到别人做的一般56层是stripe，34层是ring。能不能二者，有公用的层呢?2.关于marco生成，尤其是ram
mc生成了相关文件之后，gds和一些库文件，添加pin的时候找不到，我写过porttype那个文件的vdd，vss也加上了的，但是还是找不到。
后来用vclef导入之后就可以了找到了，但是我看手册上，也没有这个步骤啊，很费解。
vclef里面也是pin的信息而已啊，为什么还要导入这个呢?
load那个文件的时候还会报warning
>>> Read Cell LEF File "/home/jwli/design/astro/techlib/SRAM_old/art_hssp_2048x32/art_hssp_2048x32.vclef" ...
Starting to read LEF file ...
WARNING : Macro Cell art_hssp_2048x32 exists already, Deleting old version.
OVERLAP layer OVERLAP specified as OverlapCheck
Re-mark cell art_hssp_2048x32's type as MacroCell.
load smic186mlef的时候还会报
>>>>>>> MILKYWAY LEF IN <<<<<<<
>>> Read Tech LEF File "/home/jwli/design/astro/techlib/std_cell/lef/smic18_6lm.lef" ...
Start to load technology file .smic18_6lm.lef.tf.
Warning: CapModel sections are missing. Capacitance models should be loaded with a TLU+ file later. (TFCHK-084)
Technology file .smic18_6lm.lef.tf has been loaded successfully.
Starting to read LEF file ...
WARNING : Dummy layer POLY1 specified
WARNING : Overlap layer OVERLAP specified as OverlapCheck
Warning: Set layer METAL2 min area rule by stack via via2ts geometry area. (MWLIBP-103)
Warning: Set layer METAL3 min area rule by stack via via3ts geometry area. (MWLIBP-103)
Warning: Set layer METAL4 min area rule by stack via via4ts geometry area. (MWLIBP-103)
Warning: Set layer METAL5 min area rule by stack via via5ts geometry area. (MWLIBP-103)
Warning: TURNM1 is a turn via rule generate. It's not supported. (MWLIBP-106)
Warning: TURNM2 is a turn via rule generate. It's not supported. (MWLIBP-106)
Warning: TURNM3 is a turn via rule generate. It's not supported. (MWLIBP-106)
Warning: TURNM4 is a turn via rule generate. It's not supported. (MWLIBP-106)
Warning: TURNM5 is a turn via rule generate. It's not supported. (MWLIBP-106)
Warning: TURNM6 is a turn via rule generate. It's not supported. (MWLIBP-106)
Information: Choose site <smic18site> as unit tile. (MWLIBP-113)
这个有关系吗?
3 load tf时
Start to load technology file /home/jwli/design/astro/techlib/std_cell/apollo/tf/smic18_6lm.tf.
Warning: ContactCode 'CONT1' is missing the attribute 'unitMinResistance'. (line 480) (TFCHK-014)
Warning: ContactCode 'CONT1' is missing the attribute 'unitNomResistance'. (line 480) (TFCHK-014)
Warning: ContactCode 'CONT1' is missing the attribute 'unitMaxResistance'. (line 480) (TFCHK-014)
Warning: Cut layer 'VIA12' has a non-cross primary default ContactCode 'via1'. (line 498) (TFCHK-092)
Warning: Cut layer 'VIA23' has a non-cross primary default ContactCode 'via2'. (line 516) (TFCHK-092)
Warning: Cut layer 'VIA34' has a non-cross primary default ContactCode 'via3'. (line 534) (TFCHK-092)
Warning: Cut layer 'VIA45' has a non-cross primary default ContactCode 'via4'. (line 552) (TFCHK-092)
Warning: Layer 'METAL1' has a pitch 0.56 that does not match the recommended wire-to-via pitch 0.535 or 0.485. (TFCHK-049)
Warning: Layer 'METAL2' has a pitch 0.66 that does not match the recommended wire-to-via pitch 0.61 or 0.56. (TFCHK-049)
Warning: Layer 'METAL4' has a pitch 0.66 that does not match the recommended wire-to-via pitch 0.61 or 0.56. (TFCHK-049)
Warning: Layer 'METAL3' has a pitch 0.56 that does not match the doubled pitch 1.12 or tripled pitch 1.68. (TFCHK-050)
Warning: Layer 'METAL4' has a pitch 0.66 that does not match the doubled pitch 1.32 or tripled pitch 1.98. (TFCHK-050)
Warning: Layer 'METAL5' has a pitch 0.61 that does not match the doubled pitch 1.12 or tripled pitch 1.68. (TFCHK-050)
Warning: Layer 'METAL6' has a pitch 0.95 that does not match the doubled pitch 1.32 or tripled pitch 1.98. (TFCHK-050)
Technology file
/home/jwli/design/astro/techlib/std_cell/apollo/tf/smic18_6lm.tf has been loaded successfully.
这些有关兄弟没?
4.问题太多了，有没有更好些的教程关于ram库建立的啊?
mc生成了相关文件之后，gds和一些库文件，添加pin的时候找不到，我写过porttype那个文件的vdd，vss也加上了的，但是还是找不到。
后来用vclef导入之后就可以了找到了，但是我看手册上，也没有这个步骤啊，很费解。
vclef里面也是pin的信息而已啊，为什么还要导入这个呢?
load那个文件的时候还会报warning
>>> Read Cell LEF File "/home/jwli/design/astro/techlib/SRAM_old/art_hssp_2048x32/art_hssp_2048x32.vclef" ...
Starting to read LEF file ...
WARNING : Macro Cell art_hssp_2048x32 exists already, Deleting old version.
OVERLAP layer OVERLAP specified as OverlapCheck
Re-mark cell art_hssp_2048x32's type as MacroCell.
load smic186mlef的时候还会报
>>>>>>> MILKYWAY LEF IN <<<<<<<
>>> Read Tech LEF File "/home/jwli/design/astro/techlib/std_cell/lef/smic18_6lm.lef" ...
Start to load technology file .smic18_6lm.lef.tf.
Warning: CapModel sections are missing. Capacitance models should be loaded with a TLU+ file later. (TFCHK-084)
Technology file .smic18_6lm.lef.tf has been loaded successfully.
Starting to read LEF file ...
WARNING : Dummy layer POLY1 specified
WARNING : Overlap layer OVERLAP specified as OverlapCheck
Warning: Set layer METAL2 min area rule by stack via via2ts geometry area. (MWLIBP-103)
Warning: Set layer METAL3 min area rule by stack via via3ts geometry area. (MWLIBP-103)
Warning: Set layer METAL4 min area rule by stack via via4ts geometry area. (MWLIBP-103)
Warning: Set layer METAL5 min area rule by stack via via5ts geometry area. (MWLIBP-103)
Warning: TURNM1 is a turn via rule generate. It's not supported. (MWLIBP-106)
Warning: TURNM2 is a turn via rule generate. It's not supported. (MWLIBP-106)
Warning: TURNM3 is a turn via rule generate. It's not supported. (MWLIBP-106)
Warning: TURNM4 is a turn via rule generate. It's not supported. (MWLIBP-106)
Warning: TURNM5 is a turn via rule generate. It's not supported. (MWLIBP-106)
Warning: TURNM6 is a turn via rule generate. It's not supported. (MWLIBP-106)
Information: Choose site <smic18site> as unit tile. (MWLIBP-113)
这个有关系吗?
3 load tf时
Start to load technology file /home/jwli/design/astro/techlib/std_cell/apollo/tf/smic18_6lm.tf.
Warning: ContactCode 'CONT1' is missing the attribute 'unitMinResistance'. (line 480) (TFCHK-014)
Warning: ContactCode 'CONT1' is missing the attribute 'unitNomResistance'. (line 480) (TFCHK-014)
Warning: ContactCode 'CONT1' is missing the attribute 'unitMaxResistance'. (line 480) (TFCHK-014)
Warning: Cut layer 'VIA12' has a non-cross primary default ContactCode 'via1'. (line 498) (TFCHK-092)
Warning: Cut layer 'VIA23' has a non-cross primary default ContactCode 'via2'. (line 516) (TFCHK-092)
Warning: Cut layer 'VIA34' has a non-cross primary default ContactCode 'via3'. (line 534) (TFCHK-092)
Warning: Cut layer 'VIA45' has a non-cross primary default ContactCode 'via4'. (line 552) (TFCHK-092)
Warning: Layer 'METAL1' has a pitch 0.56 that does not match the recommended wire-to-via pitch 0.535 or 0.485. (TFCHK-049)
Warning: Layer 'METAL2' has a pitch 0.66 that does not match the recommended wire-to-via pitch 0.61 or 0.56. (TFCHK-049)
Warning: Layer 'METAL4' has a pitch 0.66 that does not match the recommended wire-to-via pitch 0.61 or 0.56. (TFCHK-049)
Warning: Layer 'METAL3' has a pitch 0.56 that does not match the doubled pitch 1.12 or tripled pitch 1.68. (TFCHK-050)
Warning: Layer 'METAL4' has a pitch 0.66 that does not match the doubled pitch 1.32 or tripled pitch 1.98. (TFCHK-050)
Warning: Layer 'METAL5' has a pitch 0.61 that does not match the doubled pitch 1.12 or tripled pitch 1.68. (TFCHK-050)
Warning: Layer 'METAL6' has a pitch 0.95 that does not match the doubled pitch 1.32 or tripled pitch 1.98. (TFCHK-050)
Technology file
/home/jwli/design/astro/techlib/std_cell/apollo/tf/smic18_6lm.tf has been loaded successfully.
这些有关兄弟没?
4.问题太多了，有没有更好些的教程关于ram库建立的啊?
ding.
1# ortsa ddddddddddddddddd
谢谢，学习了。
谢谢。学习了。
我真心求教啊～～
自己继续顶啊
谢谢。学习了。
没人来回答下?
遇到同样的问题。
我也遇到同样的问题，只能自己认真、忍着去学习了
我也希望有人能给个教程，自己研究不明白
这个问题是咋样解决的呢?真心求教啊
做ram库应该有一下几个步骤：
首先，通过MC生成gds,lef,lib等信息
然后，通过astro导入lef文件生成FRAM.view,这个包含了端口信息。
再然后导入GDS,有详细的版图信息。
最后导入lib生成的db文件，引入ram的timing和power信息。
OK了。
你的第一个问题，用第几层打ring和strap是随意的，只要满足DRC和preroute就可以。当然，一般来说因为顶层金属厚，所以习惯上用高层金属做电源。
我做前端的，救不了你