新手提问：产生FRAM产生的问题

在产生FRAM时产生如下问题：
auExtractBlockagePinVia
tarts ... -----
Processing cell [AD.CEL] ...
** (Delete Cell) ** (cell name = AD, view name = FRAM) does not exist.
(bpvExtractViaRegion) Cell (AD) is processing！...
Elapsed =0:00:00, CPU =0:00:00
Checking PG pin extraction:
WARNING : pin (VDDA) does not touch cell's right boundary
WARNING : pin (VSSA) does not touch cell's left boundary
ERROR : Cell [AD.FRAM] only 1 p/g rail is found
Marking EEQ ports in each cell:
Cell: AD.FRAM
#3001-libhost.a (host_001.c:89) during opendir
(~/wii_guitar_top/pre_data/pre_data/ad_8to1/A/FRAM,...) (1 times)
#2-libc.a (host_001.c:82) No such file or directory (1 times)
后面产生LM时出现如下情况：
#2-libc.a (host_001.c:82) No such file or directory (1 times)
WARNING : The library bus naming style has not been set, so the default '_<%d>' will be used. The dbSetLibBusNameStyle command can be used to set the library bus naming style.
WARNING : The library and db bus naming styles do not match, so the db bus naming style '[%d]' will be mapped to the library bus naming style '_<%d>'.
WARNING : Port 'a_in_<7>' missing from cell AD.FRAM
WARNING : Port 'a_in_<6>' missing from cell AD.FRAM
WARNING : Port 'a_in_<5>' missing from cell AD.FRAM
WARNING : Port 'a_in_<4>' missing from cell AD.FRAM
WARNING : Port 'a_in_<3>' missing from cell AD.FRAM
WARNING : Port 'a_in_<2>' missing from cell AD.FRAM
WARNING : Port 'a_in_<1>' missing from cell AD.FRAM
WARNING : Port 'a_in_<0>' missing from cell AD.FRAM
WARNING : Port 'chan_sel_<7>' missing from cell AD.FRAM
WARNING : Port 'chan_sel_<6>' missing from cell AD.FRAM
WARNING : Port 'chan_sel_<5>' missing from cell AD.FRAM
WARNING : Port 'chan_sel_<4>' missing from cell AD.FRAM
WARNING : Port 'chan_sel_<3>' missing from cell AD.FRAM
WARNING : Port 'chan_sel_<2>' missing from cell AD.FRAM
WARNING : Port 'chan_sel_<1>' missing from cell AD.FRAM
WARNING : Port 'chan_sel_<0>' missing from cell AD.FRAM
WARNING : DB '~/wii_guitar_top/pre_data/pre_data/ad_8to1/misc.db' is inconsistent with library.
Logic Model DB (Min) has been set to:
~/wii_guitar_top/pre_data/pre_data/ad_8to1/misc.db
Logic Model DB (Max) has been set to:
~/wii_guitar_top/pre_data/pre_data/ad_8to1/misc.db
Logic Model DB (Typical) has been set to:
~/wii_guitar_top/pre_data/pre_data/ad_8to1/misc.db
请教各位，这些问题如何解决。在此谢过大家了！

类似的问题 求教答案

是stdcell的还是macro的?

从lef 转吧， gds到fram很累的，