Tetramax run simulation的mismatch问题
时间:10-02
整理:3721RD
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我用tetramax进行功能向量的故障模拟,脚本如下:
#Tetramax Atpg scripts for c17
set messages -level expert
set message log control.log -replace
read netlist ../scr/or1200_cpu.v
read netlist/export/eda/edalib/smic/180nm/aci/sc-x/verilog/smic18.v
set build -nodelete_unused_gates -merge
run build_model or1200_cpu
#----------------------------------------------------------
#set up for ATPG
#----------------------------------------------------------
drc
add clock 0 clk
add clock 1 rst
set drc -nofile -allow_unstable
run drc
set patterns ext ../scr/cpu.vcde -strobe rising clk -strobe offset 50 ns
#----------------------------------------------------------
#Basic_scan_only
#----------------------------------------------------------
set_faults -model stuck -fault_coverage-pt_credit 100
remove faults -all
add faults -all
run simulation -sequential
但是,出现了很多mismatch问题:
24spr_cs[11](exp=0, got=X)
24spr_cs[10](exp=0, got=X)
24spr_cs[9](exp=0, got=X)
24spr_cs[8](exp=0, got=X)
24spr_cs[7](exp=0, got=X)
24spr_cs[6](exp=0, got=X)
24spr_cs[5](exp=0, got=X)
24spr_cs[4](exp=0, got=X)
24spr_cs[3](exp=0, got=X)
24spr_cs[2](exp=0, got=X)
24spr_cs[1](exp=0, got=X)
24spr_cs[0](exp=0, got=X)
24spr_we(exp=0, got=X)
Simulation completed: #patterns=25/50, #fail_pats=22(22), #failing_meas=5752(5752)
请问如何解决,谢谢!
#Tetramax Atpg scripts for c17
set messages -level expert
set message log control.log -replace
read netlist ../scr/or1200_cpu.v
read netlist/export/eda/edalib/smic/180nm/aci/sc-x/verilog/smic18.v
set build -nodelete_unused_gates -merge
run build_model or1200_cpu
#----------------------------------------------------------
#set up for ATPG
#----------------------------------------------------------
drc
add clock 0 clk
add clock 1 rst
set drc -nofile -allow_unstable
run drc
set patterns ext ../scr/cpu.vcde -strobe rising clk -strobe offset 50 ns
#----------------------------------------------------------
#Basic_scan_only
#----------------------------------------------------------
set_faults -model stuck -fault_coverage-pt_credit 100
remove faults -all
add faults -all
run simulation -sequential
但是,出现了很多mismatch问题:
24spr_cs[11](exp=0, got=X)
24spr_cs[10](exp=0, got=X)
24spr_cs[9](exp=0, got=X)
24spr_cs[8](exp=0, got=X)
24spr_cs[7](exp=0, got=X)
24spr_cs[6](exp=0, got=X)
24spr_cs[5](exp=0, got=X)
24spr_cs[4](exp=0, got=X)
24spr_cs[3](exp=0, got=X)
24spr_cs[2](exp=0, got=X)
24spr_cs[1](exp=0, got=X)
24spr_cs[0](exp=0, got=X)
24spr_we(exp=0, got=X)
Simulation completed: #patterns=25/50, #fail_pats=22(22), #failing_meas=5752(5752)
请问如何解决,谢谢!
不知兄弟问题解决没,我现在也遇到了类似的情况。
还望指教。
贴一下drc的结果先