求助：ASTRO的timing_report违例了，我不知道为什么

Astro Timing Report
*
*Tool: Astro
*Version : Y-2006.06-SP1 for IA.32 -- Thu Jul 27 13:55:01 PDT 2006
*Design: top
*Date: Mon Jul 20 12:03:59 2009
*
*********************************************************************************
*
*********************************************************************************
*
*Design Setup
*
*Analysis Type: Max Min
*Parasitic Source: from LPE
*LPE Operating Cond: Max Nom Min
*LPE Mode: Real_R_Virtual_C
*Wire Delay: Medium Effort
*Time Borrowing: Enabled
*Time Borrowing Method: Standard
*Preset/Clear Arcs: Disabled
*Recovery/Removal Arcs: Disabled
*Scan Enable: Enabled
*Inter Clock Paths: Enabled
*Default Clock: Enabled
*Ideal Network Delay: Enabled
*Mixed Clock/Signal Paths: Disabled
*Include Xtalk Induced Delay: Disabled
*Include Non-Propagated Nets: Disabled
*Include Lib Max Transition: Enabled
*Include Lib Max Capacitance: Enabled
*Ignore Clock Uncertainty: Disabled
*Ignore Propagated Clock: Enabled
*Set IO Clock Latency: Disabled
*Enable Data Check: Enabled
*Load Useful Skew From DB: Disabled
*Enable Clock Gating Checks: Disabled
*Multiple Clocks Per Register: Enabled
*Include CRPR: Disabled
*
*********************************************************************************
*
*********************************************************************************
*
*Reasons For No Optimization
*
*NDT : Don't touch net.
*IDT : Don't touch instance.
*FIX : Fixed instance.
*MDR : Multi-Driven net.
*PCP : Huge pin cap on the net.
*TRI : Tristate net.
*PRE : Preserve Logic.
*DIS : Disabled edges on the net.
*NEQ : No equivalent cells.
*
*********************************************************************************
*********************************************************************************
*
*Start point : m1\/Load_ram_addr_reg/CKN
*( Clock source SCL_CK )
*
*End point: \m1\/ram_0x32_reg[4]/D
*( Rising edge-triggered flipflop clocked by SCL_CK at CK )
*
*Clock Group : SCL_CK
*Delay Type: Max
*Slack: 45.6996(MET)
*
*********************************************************************************
Port/PinCapFanoutTrans.IncrArriReasonMaster/Net
---------------------------------------------------------------------------------
Falling edge of clock SCL_CK50.000050.0000
Clock Source delay0.000050.0000
Clock Network delay2.000052.0000
---------------------------------------------------------------------------------
m1\/Load_ram_addr_reg/CKN
0.00000.000050.0000 fDFFNSRX1
m1\/Load_ram_addr_reg/Q
0.002910.07160.455450.4554 fm1\/Load_ram_addr
U519/A0.07160.000050.4554 fCLKBUFX3
U519/Y0.026260.15100.205950.6613 fn765
U563/B0.15140.000450.6617 fNOR2BXL
U563/Y0.022350.92950.582751.2445 rn297
U252/D0.92990.000651.2451 rAND4X1
U252/Y0.006820.15650.323351.5683 rn305
U211/B0.15660.000151.5684 rNAND2XL
U211/Y0.004110.18060.095851.6642 fn304
U582/B0.18060.000051.6643 fNOR2X1
U582/Y0.051791.07410.661652.3258 rn303
U160/A1.07520.001452.3273 rCLKINVX3
U160/Y0.044080.38490.366252.6934 fn277
U205/B00.38660.002252.6956 fAO22X1
U205/Y0.004610.11550.403053.0986 fn386
\m1\/ram_0x32_reg[4]/D
0.11550.000053.0986 fDFFRX1
---------------------------------------------------------------------------------
Rising edge of clock SCL_CK100.0000100.0000
Clock Source delay0.0000100.0000
Clock Network delay2.0000102.0000
Clock Skew3.000099.0000
Setup time0.201898.7982
---------------------------------------------------------------------------------
Required time98.7982
Arrival time53.0986
---------------------------------------------------------------------------------
Slack45.6996(MET)
*********************************************************************************
*
*Start point : \m1\/state_reg[3]/CKN
*( Clock source SCL_CK )
*
*End point: \m1\/state_reg[3]/D
*( Falling edge-triggered flipflop clocked by SCL_CK at CKN )
*
*Clock Group : SCL_CK
*Delay Type: Min
*Slack: -1.7863(VIOLATED)
*
*********************************************************************************
Port/PinCapFanoutTrans.IncrArriReasonMaster/Net
---------------------------------------------------------------------------------
Falling edge of clock SCL_CK50.000050.0000
Clock Source delay0.000050.0000
---------------------------------------------------------------------------------
\m1\/state_reg[3]/CKN
0.00000.000050.0000 fDFFNSRX1
\m1\/state_reg[3]/QN
0.007320.06250.189150.1891 fn267
U295/A00.06260.000050.1891 fOAI21XL
U295/Y0.002110.04830.078350.2674 rn453
\m1\/state_reg[3]/D
0.04830.000050.2674 rDFFNSRX1
---------------------------------------------------------------------------------
Falling edge of clock SCL_CK50.000050.0000
Clock Source delay0.000050.0000
Clock Network delay2.000052.0000
Clock Skew0.000052.0000
Hold time0.053752.0537
---------------------------------------------------------------------------------
Required time52.0537
Arrival time50.2674
---------------------------------------------------------------------------------
Slack-1.7863(VIOLATED)
Timing Report summary
Paths reported= 2
Violations= 1
---------------------------------------------------------------------------------
最后这里RT比AT要大，为什么会VIOLATED?
报告的1个路径没有问题，RT-AT为正数，MET。第2个路径为什么同样就是负的呢?为什么要AT-RT呢?难但是hold time violate?
我是初学者们希望大家踊跃发言 。

hold违例，连续的的两个DFF之间存在非常短的路径

显然是hold-time violation 啊

不错的分享
正在寻找

是hold time violation沒錯~
Delay Type: Min==> hold time check
Delay Type: Max ==> setup time check

做hold优化

*Ignore Propagated Clock: Enabled

如果cts没做，不用看这个min
要不就是你设置有问题

encounter 工具里,CTS前是没有hold 优化选项的.

hold violation在做CTS前都不用管。做完CTS后，set clock propagated再report timing

hold slack =Arrival time - Required time

同意 9楼

这就是一个hold time的违例嘛，在CTS之后再看它！

這是PreCTS之前的report,只要將setup time修乾淨,
而且你如果用default option做placement 是不修hold time,
hold time一般都長完tree之後在placeOPT去修的
你可以看一下clock network delay 是 2是預估值在 sdc file裡設定的
長完tree後會有真正的值