从port到IO cell的输入端之间的delay为何如此大？
clock CLK125(rise edge)0.000.00
clock network delay (ideal)0.000.00
input external delay2.962.96
DRAM_DQS[0] (inout)12.1815.14
UIO_DDR_DQSB0/U_IO_DDRBI/EB(IOSSCP23CBSSN2M)1.3116.45
UIO_DDR_DQSB0/U_IO_DDRBI/X(IOSSCP23CBSSN2M)3.7620.21
......................
其中DRAM_DQS[0]就是一个 inout的port。从顶层的port送进来的信号直接就送给了这个IO cell (IOSSCP23CBSSN2M)。
我发现红色的部分有一个12ns以上的大延迟。而且几乎对于所有的端口（无论是inout的还是input的）都有这样的延迟。
我觉得红色部分的延迟应该是0才对吧?这个延迟也太大了。
而且这里也应该不存在负载太大的问题吧?毕竟这个不时时钟引脚。
请问哪位大虾知道这个延迟是如何产生的啊?
应该怎么下约束才能去掉这个延迟?
把log贴出来，大虾帮忙看看
Startpoint: DRAM_DQS[0]
(input port)
Endpoint: U_AXITOP/uMCTOP/U_DDRPHY/U_DDR1_R30/U_DDR1DQSRXTX_0/OBS_dqs270_reg
(rising edge-triggered flip-flop clocked by CLK135M_DDR_PHY1)
Path Group: CLK135M_DDR_PHY1
Path Type: max
PointIncrPath
------------------------------------------------------------------------------
clock (input port clock) (rise edge)0.000.00
input external delay0.000.00 r
DRAM_DQS[0] (inout)12180.8112180.81 r
UIO_DDR_DQSB0_0_/U_IO_DDRBI/EB (IOSSCP23CBSSN2M00)1311.9213492.73 r
UIO_DDR_DQSB0_0_/U_IO_DDRBI/X (IOSSCP23CBSSN2M00)3769.3517262.08 r
U_AXITOP/uMCTOP/U_DDRPHY/U_DDR1_R30/U_DDR1DQSRXTX_0/U_DDR1DQSMASK/U_i_dqs_mask/YB (SCWON2D11XCA)96.11 17358.19 f
U_AXITOP/uMCTOP/U_DDRPHY/U_DDR1_R30/U_DDR1DQSRXTX_0/U_DDR1DQSMASK/U_ODQS_INV/YB (SCWINVXH1)74.42 17432.61 r
U_AXITOP/uMCTOP/U_DDRPHY/U_DDR1_R30/U_DDR1DQSRXTX_0/U_DDR1DQS_VDLD/U_CLK0/Y (SCWBUFXH1)77.35 17509.96 r
U_AXITOP/uMCTOP/U_DDRPHY/U_DDR1_R30/U_DDR1DQSRXTX_0/U_DDR1DQS_VDLD/U_CLK1/Y (SCWBUFXH1)66.24 17576.19 r
U_AXITOP/uMCTOP/U_DDRPHY/U_DDR1_R30/U_DDR1DQSRXTX_0/U_DDR1DQS_VDLD/U_CLK2/Y (SCWBUFXH1)65.75 17641.95 r
U_AXITOP/uMCTOP/U_DDRPHY/U_DDR1_R30/U_DDR1DQSRXTX_0/U_DDR1DQS_VDLD/U_CLK3/Y (SCWBUFXH1)65.31 17707.26 r
U_AXITOP/uMCTOP/U_DDRPHY/U_DDR1_R30/U_DDR1DQSRXTX_0/U_DDR1DQS_VDLD/U_CLK4/Y (SCWBUFXH1)65.75 17773.01 r
U_AXITOP/uMCTOP/U_DDRPHY/U_DDR1_R30/U_DDR1DQSRXTX_0/U_DDR1DQS_VDLD/U_CLK5/Y (SCWBUFXH1)65.79 17838.80 r
U_AXITOP/uMCTOP/U_DDRPHY/U_DDR1_R30/U_DDR1DQSRXTX_0/U_DDR1DQS_VDLD/U_CLK6/Y (SCWBUFXH1)65.74 17904.54 r
U_AXITOP/uMCTOP/U_DDRPHY/U_DDR1_R30/U_DDR1DQSRXTX_0/U_DDR1DQS_VDLD/U_CLK7/Y (SCWBUFXH1)58.72 17963.26 r
U_AXITOP/uMCTOP/U_DDRPHY/U_DDR1_R30/U_DDR1DQSRXTX_0/U_DDR1DQS_VDLD/U_MSB1/Y (SCWMUX4XC1)144.81 18108.07 r
U_AXITOP/uMCTOP/U_DDRPHY/U_DDR1_R30/U_DDR1DQSRXTX_0/U_DDR1DQS_VDLD/U_SELOUT/Y (SCWMUX2XH1)99.06 18207.12 r
U_AXITOP/uMCTOP/U_DDRPHY/U_DDR1_R30/U_DDR1DQSRXTX_0/U_DDR90VDL/Y (SCWAND2XC1)94.49 18301.61 r
U_AXITOP/uMCTOP/U_DDRPHY/U_DDR1_R30/U_DDR1DQSRXTX_0/U_DDR90VDL_INV/YB (SCWINVXC1)49.54 18351.16 f
U_AXITOP/uMCTOP/U_DDRPHY/U_DDR1_R30/U_DDR1DQSRXTX_0/U_PREDQS270/Y (SCWMUX2XC1)115.31 18466.47 f
U_AXITOP/uMCTOP/U_DDRPHY/U_DDR1_R30/U_DDR1DQSRXTX_0/OBS_dqs270_reg/DATA (SCWFSGFFQXH1)0.00 18466.47 f
data arrival time18466.47
clock CLK135M_DDR_PHY1 (rise edge)7404.007404.00
clock network delay (ideal)148.087552.08
clock reconvergence pessimism0.007552.08
clock uncertainty-1110.606441.48
U_AXITOP/uMCTOP/U_DDRPHY/U_DDR1_R30/U_DDR1DQSRXTX_0/OBS_dqs270_reg/CLK (SCWFSGFFQXH1)6441.48 r
library setup time-331.026110.46
data required time6110.46
------------------------------------------------------------------------------
data required time6110.46
data arrival time-18466.47
------------------------------------------------------------------------------
slack (VIOLATED)-12356.01
知道inout/input驱动了多少门吗?
电容有多大?
ddr path啊，