后端面试--每日一题（054）

Which PVT condition will give the most leakage power?
那个PVT corner的leakage power最大?
难度：2

ML(max leakage)吧！

明显min撒。电压高，电阻低。

For Standard CMOS Logic
P: Low Vtn & Low Vtp
V:High VDD
T: Depends. High Temp for Square law region; Low Temp for Subtreshold region
For Memory and other mixed-signal circuit, it depends on the design

T: Depends. High Temp for Square law region; Low Temp for Subtreshold region
不懂，请教

P: FF corner
V: High voltage
T: High temp.

T应该是high temp

谢谢，改正！
P: FF corner
V: High voltage
T: High temp.

subthreshold region 的导电机制跟square law 不一样，ITD-> delay变小，leakage变大。

感谢，
是否有更详细的资料分享，想学习一下