dc综合时assign unassign是什么意思？

小弟谢了一个4bit 全加器，然后综合，
// rtl for 4bit full adder
module TST (CLK, IN1, IN2, SUM, CARRY);
output [3:0]SUM;
outputCARRY;
inputCLK;
input [3:0]IN1, IN2;
reg[3:0]SUM;
regCARRY;
integerTEMP;
initial begin
SUM = 0;
CARRY = 0;
end
always @(posedge CLK) begin
TEMP = IN1+IN2;
SUM = TEMP;
if (TEMP > 15)
CARRY = 1;
else
CARRY = 0;
end
endmodule
elaborate后log如下：
Running PRESTO HDLC
Warning:Starting with the 2000.11-1 release, the Presto Verilog reader treats Verilog 'integer' types as signed; synthesized result may not match earlier versions of HDL Compiler. (VER-314)
Warning:../rtl/TST.v:28: unsigned to signed assignment occurs. (VER-318)
Warning:../rtl/TST.v:29: signed to unsigned assignment occurs. (VER-318)
这里面的assign unassign把我弄糊涂了，哪位大侠可以解释下?

谢谢

声明为reg类型的寄存器变量SUM为unsigned（无符号数），而integer整型变量TEMP则为有符号数(signed)。
以下赋值语句，就是有符号数和无符号数交叉赋值，产生了warning.
TEMP = IN1+IN2;
SUM = TEMP;

You should use non blocking statements

谢谢楼上两位大侠解释，小弟有点明白了。
谢谢