紧急求助PT的问题
时间：10-02
整理：3721RD
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做post-layout 后的STA分析，有好多holdtime违反，不知道改如何修正这些问题，求高手指点一下，非常感谢！
1. 有一个warning我不知道是否重要， 不是太理解他的意思，是不是说我的设计中有一些无效的timing arc呢?这会影响后面的分析吗?
report_timing -transition_time
-path full
-delay_type min
Warning: Some timing arcs have been disabled for breaking timing loops
or because of constant propagation. Use the 'report_disable_timing'
command to get the list of these disabled timing arcs. (PTE-003)
Information: Inferring 1 clock-gating checks. (PTE-017)
2. 报告了许多hold-time的violations（astro中时序没有违反），都是如下类似的：
Startpoint: m1/u_FDCT_2D_u_FDCT_1D_1_u_piso_1/piso_out_reg_11_
(rising edge-triggered flip-flop clocked by clk_pad)
Endpoint: m1/u_FDCT_2D_u_ram_transpose_f_11_u_RF2SH_16
(rising edge-triggered flip-flop clocked by clk_pad)
Path Group: clk_pad
Path Type: min
Point
Trans
Incr
Path
-----------------------------------------------------------------------------
clock clk_pad (rise edge)
0.00
0.00
clock network delay (propagated)
1.60
1.60
m1/u_FDCT_2D_u_FDCT_1D_1_u_piso_1/piso_out_reg_11_/CK (DFFRHQX1)
0.08
0.00
1.60 r
m1/u_FDCT_2D_u_FDCT_1D_1_u_piso_1/piso_out_reg_11_/Q (DFFRHQX1)
0.06
0.19 &
1.79 f
m1/u_FDCT_2D_u_FDCT_1D_1_u_piso_1/piso_out[11] (piso_1)
0.00
0.00 &
1.79 f
m1/piso_out_reg_11_ASTttcInst2213/Y (BUFX3)
0.12
0.15 &
1.94 f
m1/u_FDCT_2D_u_ram_transpose_f_11_u_RF2SH_16/DB[11] (RF2SH_16)
0.32
0.01 &
1.95 f
data arrival time
1.95
clock clk_pad (rise edge)
0.00
0.00
clock network delay (propagated)
5.66
5.66
clock uncertainty
2.00
7.66
m1/u_FDCT_2D_u_ram_transpose_f_11_u_RF2SH_16/CLKB (RF2SH_16)
7.66 r
library hold time
0.01
7.66
data required time
7.66
-----------------------------------------------------------------------------
data required time
7.66
data arrival time
-1.95
-----------------------------------------------------------------------------
slack (VIOLATED)
-5.71
我有几点不明白：1）.高亮的clock network delay (propagated) 5.66 是怎么得到的（所有报违反的路径中这个延迟差不多都这么大），我的脚本中只设置了clock uncertainty，其它的没有设置，而得到的clock network delay怎么这么大呢?
2）. 为什么ASTRO没有修正hold-time violations呢?
3. 另外， 报告中对所有的pad都报告违反，请问这是为什么呢?需要修正吗?
Pin: data_ena_pad
max_capacitance
0.50
- Capacitance
5.44
------------------------------
Slack
-4.94
(VIOLATED)
Pin: data_ena_pad
max_transition
8.00
- Transition Time
9.65
------------------------------
Slack
-1.65
(VIOLATED)
1. 有一个warning我不知道是否重要， 不是太理解他的意思，是不是说我的设计中有一些无效的timing arc呢?这会影响后面的分析吗?
report_timing -transition_time
-path full
-delay_type min
Warning: Some timing arcs have been disabled for breaking timing loops
or because of constant propagation. Use the 'report_disable_timing'
command to get the list of these disabled timing arcs. (PTE-003)
Information: Inferring 1 clock-gating checks. (PTE-017)
2. 报告了许多hold-time的violations（astro中时序没有违反），都是如下类似的：
Startpoint: m1/u_FDCT_2D_u_FDCT_1D_1_u_piso_1/piso_out_reg_11_
(rising edge-triggered flip-flop clocked by clk_pad)
Endpoint: m1/u_FDCT_2D_u_ram_transpose_f_11_u_RF2SH_16
(rising edge-triggered flip-flop clocked by clk_pad)
Path Group: clk_pad
Path Type: min
Point
Trans
Incr
Path
-----------------------------------------------------------------------------
clock clk_pad (rise edge)
0.00
0.00
clock network delay (propagated)
1.60
1.60
m1/u_FDCT_2D_u_FDCT_1D_1_u_piso_1/piso_out_reg_11_/CK (DFFRHQX1)
0.08
0.00
1.60 r
m1/u_FDCT_2D_u_FDCT_1D_1_u_piso_1/piso_out_reg_11_/Q (DFFRHQX1)
0.06
0.19 &
1.79 f
m1/u_FDCT_2D_u_FDCT_1D_1_u_piso_1/piso_out[11] (piso_1)
0.00
0.00 &
1.79 f
m1/piso_out_reg_11_ASTttcInst2213/Y (BUFX3)
0.12
0.15 &
1.94 f
m1/u_FDCT_2D_u_ram_transpose_f_11_u_RF2SH_16/DB[11] (RF2SH_16)
0.32
0.01 &
1.95 f
data arrival time
1.95
clock clk_pad (rise edge)
0.00
0.00
clock network delay (propagated)
5.66
5.66
clock uncertainty
2.00
7.66
m1/u_FDCT_2D_u_ram_transpose_f_11_u_RF2SH_16/CLKB (RF2SH_16)
7.66 r
library hold time
0.01
7.66
data required time
7.66
-----------------------------------------------------------------------------
data required time
7.66
data arrival time
-1.95
-----------------------------------------------------------------------------
slack (VIOLATED)
-5.71
我有几点不明白：1）.高亮的clock network delay (propagated) 5.66 是怎么得到的（所有报违反的路径中这个延迟差不多都这么大），我的脚本中只设置了clock uncertainty，其它的没有设置，而得到的clock network delay怎么这么大呢?
2）. 为什么ASTRO没有修正hold-time violations呢?
3. 另外， 报告中对所有的pad都报告违反，请问这是为什么呢?需要修正吗?
Pin: data_ena_pad
max_capacitance
0.50
- Capacitance
5.44
------------------------------
Slack
-4.94
(VIOLATED)
Pin: data_ena_pad
max_transition
8.00
- Transition Time
9.65
------------------------------
Slack
-1.65
(VIOLATED)
个人觉得要修正，应该是cts没有做好，skew 造成的。具体看下clock path delay .
false path要设置好的
PT中报的准一点吧，可以按照PT里面报的HOLD违规在ASTRO里面修吧