请教PT后的violation
Startpoint: m1/u_IDCT_2D/u_IDCT_1D_2/u_mul_c1c7_13/reg_1_1_reg_1_
(rising edge-triggered flip-flop clocked by clk_pad)
Endpoint: m1/u_IDCT_2D/u_IDCT_1D_2/u_mul_c1c7_13/reg_2_1_reg_1_
(rising edge-triggered flip-flop clocked by clk_pad)
Path Group: clk_pad
Path Type: min
PointIncrPath
------------------------------------------------------------------------------
clock clk_pad (rise edge)0.000.00
clock network delay (propagated)1.661.66
m1/u_IDCT_2D/u_IDCT_1D_2/u_mul_c1c7_13/reg_1_1_reg_1_/CK (DFFRHQX1)
0.001.66 r
m1/u_IDCT_2D/u_IDCT_1D_2/u_mul_c1c7_13/reg_1_1_reg_1_/Q (DFFRHQX1)
0.19 &1.85 f
m1/u_IDCT_2D/u_IDCT_1D_2/u_mul_c1c7_13/reg_2_1_reg_1_/D (DFFRHQX4)
0.00 &1.85 f
data arrival time1.85
clock clk_pad (rise edge)0.000.00
clock network delay (propagated)5.625.62
m1/u_IDCT_2D/u_IDCT_1D_2/u_mul_c1c7_13/reg_2_1_reg_1_/CK (DFFRHQX4)
5.62 r
library hold time-0.045.58
data required time5.58
------------------------------------------------------------------------------
data required time5.58
data arrival time-1.85
------------------------------------------------------------------------------
slack (VIOLATED)-3.73
1 根据 path type来看这是一个holdtime violation (其实看路径这么短应该也能猜出这个不是setup问题了)
2 astro没报，pt报了 应该是工具的差异性问题（但是这个路径比较搞，触发器到触发器，中间没有任何逻辑?）
3 如何解决，在astro里把set_min_delay再设大一点，并且向前端反馈打空拍的问题
谢谢楼上 不好意思 这几天一直没时间上网
这个路径我查过了 就是触发器到触发器
请问set_min_delay 是指对于什么的设置呢?是input_delay吗?
前端反馈打空拍又是指什么呢?不太明白，请指教
clock network delay (propagated)5.625.62
这个延时太大了，你把这个报详细的看看
report_timing 时，将clock path展开，若公共路径延时不一样，check holdtime 时，set timing_remove_clock_reconvergence_pessimism true ；再者，就在寄存器之间插入buffer
展开以后是这样的，两个clock network delay的延迟不一样，而且P1/Y (PICS)的延迟也不一样，请问这是什么原因造成的呢?是不是设置这个set timing_remove_clock_reconvergence_pessimism true 就可以去除呢?
Startpoint: m1/rst_reg_reg
(rising edge-triggered flip-flop clocked by clk_pad)
Endpoint: m1/u_FDCT_2D_u_FDCT_1D_2_u_delay_6clk_2_data_out_2_reg_10_
(removal check against rising-edge clock clk_pad)
Path Group: **async_default**
Path Type: min
PointIncrPath
------------------------------------------------------------------------------
clock clk_pad (rise edge)0.000.00
clock source latency0.000.00
clk_pad (in)0.00 &0.00 r
P1/Y (PICS)0.52 *0.52 r
m1/BUFX20G2B1I1_1/Y (BUFX20)0.06 *0.57 r
m1/CLKBUFX20G2B2I1/Y (CLKBUFX20)0.06 *0.64 r
m1/CLKBUFX20G2B3I2/Y (CLKBUFX16)0.09 *0.73 r
m1/BUFX20G2B4I4_1/Y (BUFX20)0.07 *0.80 r
m1/BUFX20G2B5I8/Y (BUFX20)0.07 *0.87 r
m1/CLKBUFX16G2B6I17/Y (CLKBUFX16)0.08 *0.96 r
m1/BUFX20G2B7I81/Y (BUFX20)0.07 *1.03 r
m1/rst_reg_reg/CK (DFFX1)0.00 *1.03 r
m1/rst_reg_reg/Q (DFFX1)0.27 *1.30 r
m1/rst_reg_regASThfnInst1469/Y (CLKBUFX8)0.12 *1.42 r
m1/rst_reg_regASThfnInst1586/Y (BUFX3)0.15 *1.57 r
m1/rst_reg_regASThfnInst1584/Y (BUFX3)0.12 *1.68 r
m1/rst_reg_regASThfnInst1542/Y (BUFX3)0.10 *1.78 r
m1/u_FDCT_2D_u_FDCT_1D_2_u_delay_6clk_2_data_out_2_reg_10_/RN (DFFRHQX1)
0.00 *1.79 r
data arrival time1.79
clock clk_pad (rise edge)0.000.00
clock source latency4.004.00
clk_pad (in)0.00 &4.00 r
P1/Y (PICS)1.65 *5.65 r
m1/BUFX20G2B1I1_1/Y (BUFX20)0.12 *5.76 r
m1/CLKBUFX20G2B2I1/Y (CLKBUFX20)0.15 *5.92 r
m1/BUFX20G2B3I1/Y (BUFX16)0.20 *6.12 r
m1/BUFX20G2B4I2_1/Y (CLKBUFX20)0.20 *6.32 r
m1/BUFX16G2B5I4/Y (CLKBUFX12)0.22 *6.54 r
m1/BUFX20G2B6I2/Y (BUFX20)0.19 *6.73 r
m1/BUFX20G2B7I4/Y (BUFX20)0.18 *6.91 r
m1/u_FDCT_2D_u_FDCT_1D_2_u_delay_6clk_2_data_out_2_reg_10_/CK (DFFRHQX1)
0.01 *6.92 r
library removal time0.006.92
data required time6.92
------------------------------------------------------------------------------
data required time6.92
data arrival time-1.79
------------------------------------------------------------------------------
slack (VIOLATED)-5.14
P&R 与 PT的设置要一致，估计你在P&R时没有要求check reset recovery removal,而PT将这个参数打开了