新手问综合问题

Startpoint: b_reg (rising edge-triggered flip-flop clocked by clock)
Endpoint: U1 (falling edge-triggered data to data check clocked by clock)
Path Group: clock
Path Type: max
Des/Clust/PortWire Load ModelLibrary
------------------------------------------------
test05x05class
PointIncrPath
-----------------------------------------------------------
clock clock (rise edge)0.000.00
clock network delay (ideal)0.000.00
b_reg/CP (FD1)0.000.00 r
b_reg/Q (FD1)1.441.44 f
U1/B (MY_ANALOG_CELL)0.001.44 f
data arrival time1.44
clock clock (rise edge)0.000.00
clock network delay (ideal)0.000.00
a_reg/CP (FD1)0.000.00 r
a_reg/Q (FD1)1.441.44 f
U1/A (MY_ANALOG_CELL)0.001.44 f
data check setup time0.602.04
data required time2.04
-----------------------------------------------------------
data required time2.04
data arrival time-1.44
-----------------------------------------------------------
slack (MET)0.60

Startpoint: b_reg (rising edge-triggered flip-flop clocked by clock)
Endpoint: U1 (falling edge-triggered data to data check clocked by clock)
Path Group: clock
Path Type: max
Des/Clust/PortWire Load ModelLibrary
------------------------------------------------
test05x05class
PointIncrPath
-----------------------------------------------------------
clock clock (rise edge)0.000.00
clock network delay (ideal)0.000.00
b_reg/CP (FD1)0.000.00 r
b_reg/Q (FD1)1.441.44 f
U1/B (MY_ANALOG_CELL)0.001.44 f
data arrival time1.44
clock clock (rise edge)0.000.00
clock network delay (ideal)0.000.00
a_reg/CP (FD1)0.000.00 r
a_reg/Q (FD1)1.441.44 f
U1/A (MY_ANALOG_CELL)0.001.44 f
data check setup time0.602.04
data required time2.04
-----------------------------------------------------------
data required time2.04
data arrival time-1.44
-----------------------------------------------------------
slack (MET)0.60
综合报告中的r，f应该是rising和falling的意思吧，但是我用到的寄存器都是上升沿出发的啊，为什么会出来falling edge呢?不太明白，刚学综合希望大家帮帮忙啊，谢谢

buhaoyisi，第二条路径贴错了。重贴
Startpoint: b_reg (rising edge-triggered flip-flop clocked by clock)
Endpoint: U1 (rising edge-triggered data to data check clocked by clock)
Path Group: clock
Path Type: max
Des/Clust/PortWire Load ModelLibrary
------------------------------------------------
test05x05class
PointIncrPath
-----------------------------------------------------------
clock clock (rise edge)0.000.00
clock network delay (ideal)0.000.00
b_reg/CP (FD1)0.000.00 r
b_reg/Q (FD1)1.291.29 r
U1/B (MY_ANALOG_CELL)0.001.29 r
data arrival time1.29
clock clock (rise edge)0.000.00
clock network delay (ideal)0.000.00
a_reg/CP (FD1)0.000.00 r
a_reg/Q (FD1)1.291.29 r
U1/A (MY_ANALOG_CELL)0.001.29 r
data check setup time0.601.89
data required time1.89
-----------------------------------------------------------
data required time1.89
data arrival time-1.29
-----------------------------------------------------------
slack (MET)0.60
在这条path中，b_reg是rising的，之前的path中是falling的

没人?自己顶吧