Sun Microsystems phone interview questions
时间：10-02
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I have a phone interview with Sun Microsystems last week.
Here is some questions they asked.
Hopefully, someone will need it.
1. How many inputs can we have for a NAND gate in the modern technology?Why?
2. How to reduce clock skew?
3. How to design a circuit that can detect "001"?
4. How to size a 6T SRAM cell?
5. What's the relationship between Noise Margin and Beta ratio?
6. You have a static NAND gate connected by a inverter. ( It becomes AND function)
We know that the size for the inverter is NMOS: 5u, PMOS:10u.
Base on fanout 4, what's the size of each MOS in the NAND gate?
7. What's the different between Flip Flop and Latch? What's difference between their setup time?
Here is some questions they asked.
Hopefully, someone will need it.
1. How many inputs can we have for a NAND gate in the modern technology?Why?
2. How to reduce clock skew?
3. How to design a circuit that can detect "001"?
4. How to size a 6T SRAM cell?
5. What's the relationship between Noise Margin and Beta ratio?
6. You have a static NAND gate connected by a inverter. ( It becomes AND function)
We know that the size for the inverter is NMOS: 5u, PMOS:10u.
Base on fanout 4, what's the size of each MOS in the NAND gate?
7. What's the different between Flip Flop and Latch? What's difference between their setup time?
thanks for your infornation