求助，关于SRAM设计中出现latch

我设计了一个SRAM，可是结果出现了8个12bit的latch，不知道怎么消去，还望高手帮忙，在此先谢过了
！代码如下：
module SRAM(CLK, CS, AWE, A, D, AOE);
input CLK;
input CS;
input AWE;
input [2:0] A;
inout [11:0] D;
input AOE;

reg [11:0] MEM [7:0];


//Only CS is low and AWE is high,then read option is valid！
assign D = (((！CS) && AWE)==1)?MEM[A]:12'bz;
//Only AOE is low,then output data stored in the RAM to the inner FPGA modoule.
assign D = ((CLK && (！AOE))==1)?MEM[A]:12'bz;

always @(CS or AWE or A or D)
begin
if((！CS) && (！AWE))//Only CS and AWE are low,then write option is
valid！
begin
MEM[A] = D;
end
else MEM[A] = MEM[A];
end
endmodule

您在always @(CS or AWE or A or D)的括号里没有写posedge clk

我改成always @(CLK or CS or AWE or A or D)了。我是设计异步存储器，写的时候不需要判断CLK信号，还有别的什么方法么?先谢谢您了！还是有下面的warning。
WARNING:Xst:737 - Found 12-bit latch for signal <MEM_7>.
WARNING:Xst:737 - Found 12-bit latch for signal <MEM_6>.
WARNING:Xst:737 - Found 12-bit latch for signal <MEM_5>.
WARNING:Xst:737 - Found 12-bit latch for signal <MEM_4>.
WARNING:Xst:737 - Found 12-bit latch for signal <MEM_3>.
WARNING:Xst:737 - Found 12-bit latch for signal <MEM_2>.
WARNING:Xst:737 - Found 12-bit latch for signal <MEM_1>.
WARNING:Xst:737 - Found 12-bit latch for signal <MEM_0>.
Found 12-bit tristate buffer for signal <D>.
Found 12-bit 8-to-1 multiplexer for signal <$n0000> created at line 44.
Summary:
inferred12 Multiplexer(s).
inferred24 Tristate(s).
WARNING:Xst:2040 - Unit SRAM: 12 multi-source signals are replaced by logic (pull-up yes): N11, N13, N15, N17, N19, N21, N23, N25, N27, N5, N7, N9.

你的always模块的写法就是生成latch的，所以不可避免