system generator ！

system generator ！
i need too！

system generator ！
国外有产品，将systemC的high level级的描述转化为verilog RTL。
当然不是所有的systemC都能转，只是一个子集。
还有听说过的sparc，网上有免费的，但是他只提供linux下的执行程序，不提供代码

俺想学！

Xilinx System Generator for DSP - Release version 6.3
Dear Xilinx Customer,
Welcome and thank you for choosing the Xilinx System Generator
for DSP v6.3.
This file contains information you may need before installing
the software.
What's New in v6.3
******************
* ISE 6.3i compatible

* Full support for Spartan?3, Spartan?II/IIE, Virtex?E,
Virtex?II, Virtex?II Pro and Virtex?4

* Support for multiple asynchronous clocks
* Real-time hardware co-simulation
* Increased coding capabilities with generic RTL target
* Enhanced MicroBlaze peripherals
* Verilog Netlisting
* 58 Example models in total, including 19 reference designs
Check http://testlinx/products/software/sysgen/whatsnew.htm
for more details.