如何写约束

怎么没人说呢?

帮你顶下 关注中

这只能按照你的实际需要来设置

是在dc里面么?
可以用10nscreate_clock 呀.
这样dc就会计算出setup/hold需要满足的值。

同问
同样关注中

create_clock
set_clock_uncertainty
set_clock_latency
set_input_transition
set_input_delay
set_output_delay
set_load
...

关注中！1

setup/hold time should depend on the module/chip that your design interface to.

小编说的是input delay和output delay?按60％给吧

The value of input delay and output delay can not always be 60%, they should be defined according to
logic path to or from the ports,
If the logic is be registered before it was sent to output port, the output delay can be set near to the clock period.
The same reason for input port, if the signal is registered first from ports, the input delay can be set near to clock period.
If the logic path is complex, you should assume the value .

说得对，关键是小编的问题太模糊。我只是给他一个经验值。
要想写好约束，当然要具体问题具体分析了。