xilinx pci32 logic core question？

我用ISE63综合时
发现它不支持
primitice hshsh(******,******,******,*****)
input*******,*****;
output******,******;
table
# ****************8888888: *******
..
.
.
.
endtable
endprimitive
请问是什么原因啊?
例:
//Xilinx Proprietary Primitive Cell X_FF for Verilog
//
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/versclibs/data/Attic/X_FF.v,v 1.25.2.4 2003/12/10 18:44:36 wloo Exp $
//
`timescale 1 ps/1 ps

module X_FF (O, CE, CLK, I, RST, SET);
parameter INIT = 1'b0;
output O;
input CE, CLK, I, RST, SET;
wire ni, nrst, nset, in_out;
wire in_clk_enable, ce_clk_enable, rst_clk_enable, set_clk_enable;
reg notifier;
not (ni, I);
not (nrst, RST);
not (nset, SET);
xor (in_out, I, O);
and (in_clk_enable, nrst, nset, CE);
and (ce_clk_enable, nrst, nset, in_out);
and (rst_clk_enable, CE, I);
and (set_clk_enable, CE, nrst, ni);
ffsrce (O, CLK, I, CE, SET, RST, notifier);
specify
(CLK => O) = (100:100:100, 100:100:100);
(SET => O) = (0:0:0, 0:0:0);
(RST => O) = (0:0:0, 0:0:0);
$setuphold (posedge CLK, posedge CE &&& (ce_clk_enable！=0), 0:0:0, 0:0:0, notifier);
$setuphold (posedge CLK, negedge CE &&& (ce_clk_enable！=0), 0:0:0, 0:0:0, notifier);
$setuphold (posedge CLK, posedge I &&& (in_clk_enable！=0), 0:0:0, 0:0:0, notifier);
$setuphold (posedge CLK, negedge I &&& (in_clk_enable！=0), 0:0:0, 0:0:0, notifier);
$recrem (negedge RST, posedge CLK &&& (rst_clk_enable！=0), 0:0:0, 0:0:0, notifier);
$recrem (negedge SET, posedge CLK &&& (set_clk_enable！=0), 0:0:0, 0:0:0, notifier);
$period (posedge CLK &&& CE, 0:0:0, notifier);
$width (posedge RST, 0:0:0, 0, notifier);
$width (posedge SET, 0:0:0, 0, notifier);
specparam PATHPULSE$ = 0;
endspecify
endmodule
primitive ffsrce (q, clk, d, ce, set, rst, notifier);
output q; reg q;
input clk, d, ce, set, rst, notifier;
table
//clkdcesetrstnotifierqq+;
???10?:?:1;
????1?:?:0;
(01)0100?:?:0;
(01)1100?:?:1;
(01)x100?:?:x;
(01)0x00?:0:0;
(01)1x00?:1:1;
(?)?0???:?:-;
(1?)?????:?:-;
(?0)?????:?:-;
(01)010x?:?:0;
(01)11x0?:?:1;
???0(?x)?:0:0;
???(?x)0?:1:1;
(?1)1??0?:1:1;
(?1)0?0??:0:0;
(0?)1??0?:1:1;
(0?)0?0??:0:0;
?(?)????:?:-;
??(?)???:?:-;
???(?0)??:?:-;
???x(?0)?:?:x;
???0(?0)?:?:-;
?????*:?:x;
endtable
endprimitive

xilinx pci32 logic core question?
这位大哥，能否将你用得IPcore发给我一份，我目前也需要再vertex2上面做一个PCI但是没有钱去买license麻烦你帮帮忙！谢谢！

xilinx pci32 logic core question?
我也需要一个，也送我一个吧！