modelsim se 5.7d, can it support "shared varialbe"？

I change the VHDL93=0 in modelsim.ini to VHDL93=1, but it can not compile "shared
variable".
The source file is as following:
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ram is port(
-- Inputs
clk : in std_logic; -- Clock, async reset
en, we : in std_logic; -- Sync enable, write enable
a : in std_logic_vector(5 downto 0); -- Read address
din : in std_logic_vector(7 downto 0); -- Data input bus
-- Outputs
dout : out std_logic_vector(7 downto 0) -- Data output bus
);
end ram;
architecture beh of ram is
type mram is array (39 downto 0) of std_ulogic_vector(7 downto 0);
shared variable mem : mram; -- Memory array 40x8
begin
-- Single port RAM model
process(clk)
variable n : integer;
begin
if clk'event and clk = '1' then
-- Memory is written and read synchronoulsy
-- when enabled
if en = '1' then
n:=conv_integer(a);
if n < 40 then
-- Write port
if we = '1' then
mem(n) := din;
end if;
-- Read port
dout <= mem(n);
else
dout <= "XXXXXXXX";
end if;
end if;
end if;
end process;
end beh;
The error is as following:
near "shared" : expecting : BEGIN
Why? Someone can tell me.

modelsim se 5.7d, can it support "shared varialbe"?
Why no one can tell me?